rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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librelane.json (454B)

      1 {
      2     "DESIGN_NAME": "rv32g_hart_top",
      3     "VERILOG_FILES": ["dir::rtl/rv32g_pkg.sv",
      4 		      "dir::rtl/rv32g_hart.sv",
      5 		      "dir::rtl/stage_decode.sv",
      6 		      "dir::rtl/stage_execute.sv",
      7 		      "dir::rtl/stage_fetch.sv",
      8 		      "dir::rtl/stage_memory.sv",
      9 		      "dir::rtl/stage_writeback.sv",
     10 		      "dir::rtl/unified_memory.sv",
     11 		      "dir::rtl/rv32g_hart_top.sv"],
     12     "CLOCK_PERIOD": 250,
     13     "CLOCK_PORT": "clk",
     14     "USE_SLANG": true
     15 }