rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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manifest.scm (337B)

      1 (use-modules (gnu packages base)
      2 	     (gnu packages commencement)
      3 	     (gnu packages cross-base)
      4 	     (gnu packages electronics)
      5 	     (gnu packages python))
      6 
      7 (packages->manifest (list gcc-toolchain
      8 			  gnu-make
      9 			  librelane
     10 			  nextpnr-cli
     11 			  python
     12 			  verilator
     13 			  yosys
     14 			  (cross-gcc-toolchain "riscv32-unknown-elf")))