rv32g-core

rv32g_hart.sv (9365B)

---

 module rv32g_hart
   import rv32g_pkg::*;
    (input logic		clk,
     input logic		rstN,
 
     output logic [31:0]	imem_addr,
     input logic [31:0]	imem_data,
     input logic		imem_valid,
 
     output logic [31:0]	dmem_addr,
     input logic		dmem_valid,
     input logic [31:0]	dmem_rdata,
     output logic [31:0]	dmem_wdata,
     output logic	dmem_we,
     output logic [3:0]	dmem_be,
 
     output reg_t	pc_out,
 
     output exception_t	exception);
 
    reg_t	next_pc;
 
    // pipeline registers
    ifid_reg_t	ifid_reg;
    idex_reg_t	idex_reg;
    exmem_reg_t	exmem_reg;
    memwb_reg_t	memwb_reg;
 
    // temporary fetch signals
    logic [31:0]	fetch_inst, ifid_inst, replay_inst;
    logic	replay_valid;
    reg_t	pc_reg, pc_plus4; // pre-computed registered +4 for critical path
 
    // temporary decode signals
    ctrl_t	dec_ctrl;
    reg_t	dec_pc, dec_imm, idex_rs1_val, idex_rs2_val;
    logic [4:0]	dec_rs1_num, dec_rs2_num, dec_rd_num;
 
    // temporary execute signals
    reg_t	ex_rs1_val, ex_rs2_val, ex_alu_out, ex_jalr_target, ex_wb_value;
    logic	ex_branch_taken;
 
    // temporary memory signals
    loadop_t	mem_loadop;
    storeop_t	mem_storeop;
    logic [31:0]	mem_mem_out;
    reg_t	memwb_value;
 
    // temporary writeback signals
    logic	wb_valid, wb_we;
 
    // hazards and control flow
    logic	dec_uses_rs1, dec_uses_rs2;
    forward_t	dec_rs1_forward, dec_rs2_forward;
    logic	load_use_stall;
    logic	redirect_valid;
    reg_t	redirect_target;
 
    // =============
    // === FETCH ===
    // =============
 
    assign pc_out = pc_reg;
    assign ifid_inst = replay_valid ? replay_inst : fetch_inst;
 
    stage_fetch u_fetch(.clk, .rstN, .flush_i(idex_reg.valid && idex_reg.ctrl.fence_flush),
 		       .pc(pc_reg), .imem_addr, .imem_data, .imem_valid,
 		       .inst(fetch_inst));
    // IF/ID pipeline register
    always_ff @(posedge clk) begin
      if (!rstN) begin
        pc_reg <= BASE_ADDR;
        pc_plus4 <= BASE_ADDR + 4;
        ifid_reg.valid <= 1'b0;
        replay_valid <= 1'b0;
      end else if (redirect_valid) begin
        pc_reg <= redirect_target;
        pc_plus4 <= redirect_target + 4;
        ifid_reg.valid <= 1'b0;
        replay_valid <= 1'b0;
      end else if (load_use_stall) begin
        if (!replay_valid) replay_inst <= fetch_inst;
        replay_valid <= 1'b1;
      end else begin
        pc_reg <= next_pc;
        pc_plus4 <= next_pc + 4;
        ifid_reg.valid <= 1'b1;
        ifid_reg.pc <= pc_reg;
        replay_valid <= 1'b0;
      end
    end
 
    // ==============
    // === DECODE ===
    // ==============
 
    stage_decode u_decode(.clk, .rstN, .inst(ifid_inst),
 			 .wb_we, .wb_rd_num(memwb_reg.rd_num), .wb_data(memwb_value),
 			 .ctrl(dec_ctrl), .imm(dec_imm),
 			 .rs1_num(dec_rs1_num), .rs2_num(dec_rs2_num),
 			 .rs1_val(idex_rs1_val), .rs2_val(idex_rs2_val),
 			 .rd_num(dec_rd_num));
 
    // assign control hazard signals
    always_comb begin
      dec_uses_rs1 = 1'b0;
      dec_uses_rs2 = 1'b0;
      dec_rs1_forward = FWD_REG;
      dec_rs2_forward = FWD_REG;
 
      unique case (opcode_t'(ifid_inst[6:0]))
        OPCODE_JALR, OPCODE_LOAD, OPCODE_OP_IMM: dec_uses_rs1 = 1'b1;
        OPCODE_BRANCH, OPCODE_STORE, OPCODE_OP: begin
          dec_uses_rs1 = 1'b1;
          dec_uses_rs2 = 1'b1;
        end
        default: ;
      endcase
 
      if (dec_uses_rs1 && dec_rs1_num != 0) begin
        if (idex_reg.valid && idex_reg.ctrl.wbsrc != WB_NONE &&
 	   idex_reg.ctrl.wbsrc != WB_MEM && idex_reg.rd_num == dec_rs1_num)
 	 dec_rs1_forward = FWD_EXMEM;
        else if (exmem_reg.valid && exmem_reg.wbsrc != WB_NONE &&
 		exmem_reg.wbsrc != WB_MEM && exmem_reg.rd_num == dec_rs1_num)
 	 dec_rs1_forward = FWD_MEMWB;
      end
 
      if (dec_uses_rs2 && dec_rs2_num != 0) begin
        if (idex_reg.valid && idex_reg.ctrl.wbsrc != WB_NONE &&
 	   idex_reg.ctrl.wbsrc != WB_MEM && idex_reg.rd_num == dec_rs2_num)
 	 dec_rs2_forward = FWD_EXMEM;
        else if (exmem_reg.valid && exmem_reg.wbsrc != WB_NONE &&
 		exmem_reg.wbsrc != WB_MEM && exmem_reg.rd_num == dec_rs2_num)
 	 dec_rs2_forward = FWD_MEMWB;
      end
 
      load_use_stall = ifid_reg.valid && imem_valid &&
 		      ((idex_reg.valid && idex_reg.ctrl.wbsrc == WB_MEM &&
 			idex_reg.rd_num != 0 &&
 			((dec_uses_rs1 && dec_rs1_num == idex_reg.rd_num) ||
 			 (dec_uses_rs2 && dec_rs2_num == idex_reg.rd_num))) ||
 		       (exmem_reg.valid && exmem_reg.wbsrc == WB_MEM &&
 			exmem_reg.rd_num != 0 &&
 			((dec_uses_rs1 && dec_rs1_num == exmem_reg.rd_num) ||
 			 (dec_uses_rs2 && dec_rs2_num == exmem_reg.rd_num))));
    end
 
    // ID/EX pipeline register
    always_ff @(posedge clk or negedge rstN) begin
      if (!rstN) begin
        idex_reg <= '0;
      end else if (redirect_valid || load_use_stall) begin
        idex_reg.valid <= 1'b0;
      end else begin
        // latch decode outputs in normal operation
        idex_reg.valid <= ifid_reg.valid && imem_valid;
        idex_reg.ctrl <= dec_ctrl;
        idex_reg.pc <= ifid_reg.pc;
        idex_reg.imm <= dec_imm;
        idex_reg.rs1_forward <= dec_rs1_forward;
        idex_reg.rs2_forward <= dec_rs2_forward;
        idex_reg.rd_num <= dec_rd_num;
      end
    end
 
    // ===============
    // === EXECUTE ===
    // ===============
 
    // select EX stage operands via forwarding from EX/MEM and MEM/WB pipeline registers
    always_comb begin
      unique case (idex_reg.ctrl.wbsrc)
        WB_PC: ex_wb_value = idex_reg.pc + 4;
        WB_ALU: ex_wb_value = ex_alu_out;
        WB_IMM: ex_wb_value = idex_reg.imm;
        default: ex_wb_value = '0;
      endcase
 
      memwb_value = memwb_reg.wbsrc == WB_MEM ? mem_mem_out :
 		   memwb_reg.wb_value;
 
      unique case (idex_reg.rs1_forward)
        FWD_REG: ex_rs1_val = idex_rs1_val;
        FWD_EXMEM: ex_rs1_val = exmem_reg.wb_value;
        FWD_MEMWB: ex_rs1_val = memwb_reg.wb_value;
        default: ex_rs1_val = '0;
      endcase
 
      unique case (idex_reg.rs2_forward)
        FWD_REG: ex_rs2_val = idex_rs2_val;
        FWD_EXMEM: ex_rs2_val = exmem_reg.wb_value;
        FWD_MEMWB: ex_rs2_val = memwb_reg.wb_value;
        default: ex_rs2_val = '0;
      endcase
    end
 
    stage_execute u_execute(.clk,
 			   .imm(idex_reg.imm),
 			   .pc(idex_reg.pc),
 			   .rs1_val(ex_rs1_val),
 			   .rs2_val(ex_rs2_val),
 			   .op(idex_reg.ctrl.aluop),
 			   .op1src(idex_reg.ctrl.aluop1src),
 			   .op2src(idex_reg.ctrl.aluop2src),
 			   .branchop(idex_reg.ctrl.branchop),
 			   .out(ex_alu_out),
 			   .branch_taken(ex_branch_taken),
 			   .jalr_target(ex_jalr_target));
    // EX/MEM pipeline register
    always_ff @(posedge clk or negedge rstN) begin
      if (!rstN) begin
        exmem_reg <= '0;
      end else begin
        exmem_reg.valid <= idex_reg.valid;
        exmem_reg.alu_out <= ex_alu_out;
        exmem_reg.rs2_val <= ex_rs2_val;
        exmem_reg.wb_value <= ex_wb_value;
        exmem_reg.rd_num <= idex_reg.rd_num;
        exmem_reg.branch_taken <= ex_branch_taken;
        exmem_reg.branchop <= idex_reg.ctrl.branchop;
        exmem_reg.loadop <= idex_reg.ctrl.loadop;
        exmem_reg.storeop <= idex_reg.ctrl.storeop;
        exmem_reg.wbsrc <= idex_reg.ctrl.wbsrc;
        exmem_reg.pcsrc <= idex_reg.ctrl.pcsrc;
        exmem_reg.exception <= idex_reg.ctrl.exception;
        exmem_reg.fence_flush <= idex_reg.ctrl.fence_flush;
      end
    end
 
    // resolve control transfers in EX stage and select the next PC
    always_comb begin
      redirect_valid = 1'b0;
      redirect_target = idex_reg.pc + 4;
 
      if (idex_reg.valid) begin
        if (idex_reg.ctrl.fence_flush) begin
 	 redirect_valid = 1'b1;
        end else begin
 	 unique case (idex_reg.ctrl.pcsrc)
 	   PC_IMM: begin
 	     if (idex_reg.ctrl.branchop == BRANCH_NONE || ex_branch_taken) begin
 	       redirect_valid = 1'b1;
 	       redirect_target = idex_reg.pc + idex_reg.imm;
 	     end
 	   end
 	   PC_ALU: begin
 	     redirect_valid = 1'b1;
 	     redirect_target = ex_jalr_target & ~32'b1;
 	   end
 	   default: ;
 	 endcase
        end
      end
 
      next_pc = redirect_valid ? redirect_target : pc_plus4;
    end
 
    // ==============
    // === MEMORY ===
    // ==============
 
    assign mem_loadop = memwb_reg.valid ? memwb_reg.loadop : LD_NONE;
    assign mem_storeop = exmem_reg.valid ? exmem_reg.storeop : ST_NONE;
 
    stage_memory u_mem(.loadop(mem_loadop),
 		      .storeop(mem_storeop),
 		      .addr(memwb_reg.alu_out),
 		      .alu_out(exmem_reg.alu_out),
 		      .rs2_val(exmem_reg.rs2_val),
 		      .mem_out(mem_mem_out),
 		      .dmem_addr, .dmem_rdata, .dmem_wdata, .dmem_we, .dmem_be);
    // MEM/WB pipeline register
    always_ff @(posedge clk or negedge rstN) begin
      if (!rstN) begin
        memwb_reg <= '0;
      end else begin
        memwb_reg.valid <= exmem_reg.valid;
        memwb_reg.alu_out <= exmem_reg.alu_out;
        memwb_reg.wb_value <= exmem_reg.wb_value;
        memwb_reg.rd_num <= exmem_reg.rd_num;
        memwb_reg.loadop <= exmem_reg.loadop;
        memwb_reg.storeop <= exmem_reg.storeop;
        memwb_reg.wbsrc <= exmem_reg.wbsrc;
        memwb_reg.exception <= exmem_reg.exception;
      end
    end
 
    // =================
    // === WRITEBACK ===
    // =================
 
    // assigns signals that are forwarded back to ID stage
    always_comb begin
      wb_valid = memwb_reg.valid &&
 		(memwb_reg.wbsrc != WB_MEM || dmem_valid);
      wb_we = wb_valid && memwb_reg.wbsrc != WB_NONE && memwb_reg.rd_num != 0;
    end
 
    assign exception = memwb_reg.valid ? memwb_reg.exception : EXC_NONE;
 
 endmodule: rv32g_hart