rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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rv32g_hart_top.cst (269B)

      1 IO_LOC "clk" V22;
      2 IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3;
      3 IO_LOC "rstN" E3;
      4 IO_PORT "rstN" IO_TYPE=LVCMOS33;
      5 IO_LOC "exception[0]" AB10;
      6 IO_PORT "exception[0]" IO_TYPE=LVCMOS33;
      7 IO_LOC "exception[1]" AB11;
      8 IO_PORT "exception[1]" IO_TYPE=LVCMOS33;