rv32g_hart_top.sv (886B)
1 module rv32g_hart_top 2 import rv32g_pkg::*; 3 ( input logic clk, 4 input logic rstN, 5 output exception_t exception 6 ); 7 8 // Wires connecting memory and core 9 logic [31:0] imem_addr; 10 logic [31:0] imem_data; 11 logic imem_valid; 12 logic [31:0] dmem_addr; 13 logic dmem_we; 14 logic [3:0] dmem_be; 15 logic [31:0] dmem_rdata; 16 logic [31:0] dmem_wdata; 17 logic dmem_valid; // now driven by memory 18 reg_t pc_out; 19 20 // Instantiate unified memory (modified to output dmem_valid) 21 unified_memory u_mem (.clk, .imem_addr, .imem_data, .imem_valid, 22 .dmem_addr, .dmem_we, .dmem_be, 23 .dmem_wdata, .dmem_rdata, .dmem_valid); 24 25 // Instantiate the core 26 rv32g_hart dut (.clk, .rstN, .pc_out, .exception, 27 .imem_addr, .imem_data, .imem_valid, 28 .dmem_addr, .dmem_valid, 29 .dmem_rdata, .dmem_wdata, 30 .dmem_we, .dmem_be); 31 32 endmodule : rv32g_hart_top