rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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rv32g_pkg.sv (4791B)


      1 package rv32g_pkg;
      2    parameter BASE_ADDR = 32'h8000_0000;
      3    parameter CACHE_DEPTH = 8192;
      4    //parameter CACHE_DEPTH = 64;
      5 
      6    typedef logic [31:0]	reg_t;
      7 
      8    typedef enum logic [3:0] {INVALIDTYPE,
      9 			     RTYPE,
     10 			     ITYPE,
     11 			     STYPE,
     12 			     BTYPE,
     13 			     UTYPE,
     14 			     JTYPE}
     15      inst_type_t;
     16 
     17    // based off of Unprivileged ISA Chapter 36 Table 72 (no reserved)
     18    typedef enum logic [6:0] {OPCODE_INVALID = 'b0000000,
     19 			     // rv32i/m
     20 			     OPCODE_LUI = 'b0110111,
     21 			     OPCODE_AUIPC = 'b0010111,
     22 			     OPCODE_JAL = 'b1101111,
     23 			     OPCODE_JALR = 'b1100111,
     24 			     OPCODE_BRANCH = 'b1100011,
     25 			     OPCODE_LOAD = 'b0000011,
     26 			     OPCODE_STORE = 'b0100011,
     27 			     OPCODE_OP_IMM = 'b0010011,
     28 			     OPCODE_OP = 'b0110011,
     29 			     OPCODE_MISC_MEM = 'b0001111,
     30 			     OPCODE_SYSTEM = 'b1110011,
     31 			     // rv32f/d
     32 			     OPCODE_LOAD_FP = 'b0000111,
     33 			     OPCODE_STORE_FP = 'b0100111,
     34 			     OPCODE_OP_FP = 'b1010011,
     35 			     OPCODE_MADD = 'b1000011,
     36 			     OPCODE_MSUB = 'b1000111,
     37 			     OPCODE_NMADD = 'b1001111,
     38 			     OPCODE_NMSUB = 'b1001011,
     39 			     // rv32a
     40 			     OPCODE_AMO = 'b0101111,
     41 			     // rv32v
     42 			     OPCODE_OP_V = 'b1010111,
     43 			     OPCODE_OP_VE = 'b1110111,
     44 			     // custom
     45 			     OPCODE_CUSTOM_0 = 'b0001011,
     46 			     OPCODE_CUSTOM_1 = 'b0101011,
     47 			     OPCODE_CUSTOM_2 = 'b1011011,
     48 			     OPCODE_CUSTOM_3 = 'b1111011}
     49 					      opcode_t;
     50 
     51    typedef enum logic [3:0] {// rv32i
     52 			     ALU_NONE,
     53 			     ALU_ADD,
     54 			     ALU_SUB,
     55 			     ALU_XOR,
     56 			     ALU_OR,
     57 			     ALU_AND,
     58 			     ALU_SLL,
     59 			     ALU_SRL,
     60 			     ALU_SRA,
     61 			     ALU_SLT,
     62 			     ALU_SLTU
     63 			     // TODO rv32m
     64 			     // ALU_MUL,
     65 			     // ALU_DIV,
     66 			     // ALU_REM,
     67 			     // TODO rv32a
     68 			     // TODO rv32f
     69 			     // TODO rv32d
     70 			     } aluop_t;
     71 
     72    typedef enum logic [1:0] {ALUOP1_NONE,
     73 			     ALUOP1_REG, // pretty much every intruction except AUIPC
     74 			     ALUOP1_PC   // AUIPC is special :)
     75 			     } aluop1src_t;
     76 
     77    typedef enum logic [1:0] {ALUOP2_NONE,
     78 			     ALUOP2_REG, // R-type and S-type instructions
     79 			     ALUOP2_IMM  // sign-extended immediate for I-type and JALR
     80 			     } aluop2src_t;
     81 
     82    typedef enum logic [2:0] {LD_LB = 3'b000,
     83 			     LD_LH = 3'b001,
     84 			     LD_LW = 3'b010,
     85 			     LD_LBU = 3'b100,
     86 			     LD_LHU = 3'b101,
     87 			     LD_NONE = 3'b111
     88 			     } loadop_t;
     89 
     90    typedef enum logic [2:0] {ST_SB,
     91 			     ST_SH,
     92 			     ST_SW,
     93 			     ST_NONE} storeop_t;
     94 
     95    typedef enum logic [2:0] {BRANCH_BEQ = 3'b000,
     96 			     BRANCH_BNE = 3'b001,
     97 			     BRANCH_BLT = 3'b100,
     98 			     BRANCH_BGE = 3'b101,
     99 			     BRANCH_BLTU = 3'b110,
    100 			     BRANCH_BGEU = 3'b111,
    101 			     BRANCH_NONE = 3'b011 // this value is unused.
    102 			     } branchop_t;
    103 
    104    typedef enum logic [1:0] {PC_SEQ, // PC = PC + 4 (regular)
    105 			     PC_IMM, // PC = PC + imm (branch and jal)
    106 			     PC_ALU  // PC = rs1 + imm (jalr)
    107 			     } pcsrc_t;
    108 
    109    typedef enum logic [2:0] {WB_NONE, // no register writeback
    110 			     WB_PC,   // JAL/R writes using PC adder, i.e. rd = pc + 4
    111 			     WB_ALU,  // R-type and I-type instructions
    112 			     WB_MEM,  // All load instructions
    113 			     WB_IMM   // LUI writes back an immediate value
    114 			     } wbsrc_t;
    115 
    116    typedef enum logic [1:0] {FWD_REG,
    117 			     FWD_EXMEM,
    118 			     FWD_MEMWB
    119 			     } forward_t;
    120 
    121    // very rudimentary. privileged spec (chapter 3) defines this formally, but left to implementation
    122    // on unprivileged spec.
    123    typedef enum logic [1:0] {EXC_NONE,
    124 			     EXC_ILL_INST, // illegal instruction
    125 			     EXC_CALL,	   // ECALL
    126 			     EXC_BKPT	   // EBREAK
    127 			     } exception_t;
    128 
    129    typedef struct packed {
    130      aluop_t	 aluop;
    131      aluop1src_t aluop1src;
    132      aluop2src_t aluop2src;
    133      loadop_t	 loadop;
    134      storeop_t	 storeop;
    135      pcsrc_t	 pcsrc;
    136      branchop_t	 branchop;
    137      wbsrc_t	 wbsrc;
    138      exception_t exception;
    139      logic	 fence_flush;
    140    } ctrl_t;
    141 
    142    // pipeline registers
    143    typedef struct packed {
    144      logic	  valid;
    145      reg_t	  pc;
    146    } ifid_reg_t;
    147 
    148    typedef struct packed {
    149      logic	  valid;
    150      ctrl_t	  ctrl;
    151      reg_t	  pc;
    152      logic [31:0] imm;
    153      forward_t	  rs1_forward;
    154      forward_t	  rs2_forward;
    155      logic [4:0]  rd_num;
    156    } idex_reg_t;
    157 
    158    typedef struct packed {
    159      logic	 valid;
    160      reg_t	 alu_out;
    161      reg_t	 rs2_val;
    162      reg_t	 wb_value;
    163      logic [4:0] rd_num;
    164      logic	 branch_taken;
    165      branchop_t  branchop;
    166      loadop_t	 loadop;
    167      storeop_t	 storeop;
    168      wbsrc_t	 wbsrc;
    169      pcsrc_t	 pcsrc;
    170      exception_t exception;
    171      logic	 fence_flush;
    172    } exmem_reg_t;
    173 
    174    typedef struct packed {
    175      logic	 valid;
    176      reg_t	 alu_out;
    177      reg_t	 wb_value;
    178      logic [4:0] rd_num;
    179      loadop_t	 loadop;
    180      storeop_t	 storeop;
    181      wbsrc_t	 wbsrc;
    182      exception_t exception;
    183    } memwb_reg_t;
    184 endpackage: rv32g_pkg