rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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stage_execute.sv (1752B)


      1 module stage_execute
      2   import rv32g_pkg::*;
      3    (input logic		clk,
      4     input aluop_t	op,
      5     input aluop1src_t	op1src,
      6     input aluop2src_t	op2src,
      7     input branchop_t	branchop,
      8     input logic [31:0]	imm,
      9     input reg_t		pc,
     10     input reg_t		rs1_val,
     11     input reg_t		rs2_val,
     12     output logic [31:0]	out,
     13     output logic	branch_taken,
     14     output logic [31:0]	jalr_target);
     15 
     16    reg_t       a, b;
     17    logic [4:0] shamt;
     18 
     19    always_comb begin
     20      // assign inputs
     21      unique case (op1src)
     22        ALUOP1_NONE: a = '0;
     23        ALUOP1_REG: a = rs1_val;
     24        ALUOP1_PC: a = pc;
     25      endcase
     26      unique case (op2src)
     27        ALUOP2_NONE: b = '0;
     28        ALUOP2_REG: b = rs2_val;
     29        ALUOP2_IMM: b = imm;
     30      endcase
     31 
     32      shamt = b[4:0];
     33 
     34      // perform computation
     35      unique case (op)
     36        ALU_NONE: out = '0;
     37        ALU_ADD: out = a + b;
     38        ALU_SUB: out = $signed(a) - $signed(b);
     39        ALU_XOR: out = a ^ b;
     40        ALU_OR: out = a | b;
     41        ALU_AND: out = a & b;
     42        ALU_SLL: out = a << shamt;
     43        ALU_SRL: out = a >> shamt;
     44        ALU_SRA: out = $signed(a) >>> shamt;
     45        ALU_SLT: out = ($signed(a) < $signed(b)) ? 1 : 0;
     46        ALU_SLTU: out = (a < b) ? 1 : 0;
     47      endcase
     48 
     49      jalr_target = rs1_val + imm;
     50 
     51      // check if branch should be taken
     52      unique case (branchop)
     53        BRANCH_NONE: branch_taken = 0;
     54        BRANCH_BEQ: branch_taken = rs1_val == rs2_val;
     55        BRANCH_BNE: branch_taken = rs1_val != rs2_val;
     56        BRANCH_BLT: branch_taken = $signed(rs1_val) < $signed(rs2_val);
     57        BRANCH_BGE: branch_taken = $signed(rs1_val) >= $signed(rs2_val);
     58        BRANCH_BLTU: branch_taken = rs1_val < rs2_val;
     59        BRANCH_BGEU: branch_taken = rs1_val >= rs2_val;
     60      endcase
     61    end  
     62 
     63 endmodule: stage_execute