rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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stage_writeback.sv (736B)

      1 module stage_writeback
      2   import rv32g_pkg::*;
      3    (input logic	      clk,
      4     input logic	      rstN,
      5     input logic       valid,
      6     input wbsrc_t     wbsrc,
      7     input logic [4:0] rd_num,
      8     input reg_t	      pc,
      9     input reg_t	      imm,
     10     input reg_t	      alu_out,
     11     input reg_t	      mem_out,
     12     output reg_t      regfile [0:31]);
     13 
     14    always_ff @(posedge clk or negedge rstN) begin
     15      if (!rstN) begin
     16        foreach (regfile[i]) regfile[i] <= '0;
     17      end else if (valid && rd_num != 0) begin
     18        unique case (wbsrc)
     19 	 WB_NONE: ;
     20 	 WB_PC: regfile[rd_num] <= pc + 4;
     21 	 WB_ALU: regfile[rd_num] <= alu_out;
     22 	 WB_MEM: regfile[rd_num] <= mem_out;
     23 	 WB_IMM: regfile[rd_num] <= imm;
     24        endcase
     25      end
     26    end
     27 
     28 endmodule