rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
Log | Files | Refs | LICENSE

link.ld (296B)

      1 OUTPUT_ARCH( "riscv" )
      2 ENTRY(_start)
      3 
      4 SECTIONS
      5 {
      6   /* . = 0x80000000; */
      7   . = 0x00000000;
      8   .text.init : { *(.text.init) }
      9   . = ALIGN(0x1000);
     10   .tohost : { *(.tohost) }
     11   . = ALIGN(0x1000);
     12   .text : { *(.text) }
     13   . = ALIGN(0x1000);
     14   .data : { *(.data) }
     15   .bss : { *(.bss) }
     16   _end = .;
     17 }
     18