rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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riscv_test.h (4952B)

      1 // See LICENSE for license details.
      2 
      3 #ifndef _ENV_PHYSICAL_SINGLE_CORE_H
      4 #define _ENV_PHYSICAL_SINGLE_CORE_H
      5 
      6 //-----------------------------------------------------------------------
      7 // Begin Macro
      8 //-----------------------------------------------------------------------
      9 
     10 #define RVTEST_RV32U                                                    \
     11   .macro init;                                                          \
     12   .endm
     13 #define RVTEST_RV64U RVTEST_RV32U
     14 
     15 #define RVTEST_RV32UF                                                   \
     16   .macro init;                                                          \
     17   .endm
     18 #define RVTEST_RV64UF RVTEST_RV32UF
     19 #define TEST_FP_INT_OP_D TEST_FP_INT_OP_D32
     20 
     21 #define RVTEST_RV32UV                                                   \
     22   .macro init;                                                          \
     23   RVTEST_VECTOR_ENABLE;                                                 \
     24   .endm
     25 #define RVTEST_RV64UV RVTEST_RV32UV
     26 
     27 #define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
     28 
     29 #define INIT_XREG                                                       \
     30   li x1, 0;                                                             \
     31   li x2, 0;                                                             \
     32   li x3, 0;                                                             \
     33   li x4, 0;                                                             \
     34   li x5, 0;                                                             \
     35   li x6, 0;                                                             \
     36   li x7, 0;                                                             \
     37   li x8, 0;                                                             \
     38   li x9, 0;                                                             \
     39   li x10, 0;                                                            \
     40   li x11, 0;                                                            \
     41   li x12, 0;                                                            \
     42   li x13, 0;                                                            \
     43   li x14, 0;                                                            \
     44   li x15, 0;                                                            \
     45   li x16, 0;                                                            \
     46   li x17, 0;                                                            \
     47   li x18, 0;                                                            \
     48   li x19, 0;                                                            \
     49   li x20, 0;                                                            \
     50   li x21, 0;                                                            \
     51   li x22, 0;                                                            \
     52   li x23, 0;                                                            \
     53   li x24, 0;                                                            \
     54   li x25, 0;                                                            \
     55   li x26, 0;                                                            \
     56   li x27, 0;                                                            \
     57   li x28, 0;                                                            \
     58   li x29, 0;                                                            \
     59   li x30, 0;                                                            \
     60   li x31, 0;
     61 
     62 #define RVTEST_CODE_BEGIN                                               \
     63         .section .text.init;                                            \
     64         .align  2;                                                      \
     65         .globl _start;                                                  \
     66 _start:                                                                 \
     67         INIT_XREG;                                                      \
     68         li TESTNUM, 0;                                                  \
     69         init;                                                           \
     70 1:
     71 
     72 //-----------------------------------------------------------------------
     73 // End Macro
     74 //-----------------------------------------------------------------------
     75 
     76 #define RVTEST_CODE_END                                                 \
     77         unimp
     78 
     79 //-----------------------------------------------------------------------
     80 // Pass/Fail Macro
     81 //-----------------------------------------------------------------------
     82 
     83 #define RVTEST_PASS                                                     \
     84         fence;                                                          \
     85 	ecall;
     86 
     87 
     88 #define TESTNUM gp
     89 #define RVTEST_FAIL                                                     \
     90         fence;                                                          \
     91 	ebreak;
     92 
     93 //-----------------------------------------------------------------------
     94 // Data Section Macro
     95 //-----------------------------------------------------------------------
     96 
     97 #define RVTEST_DATA_BEGIN .align 4;
     98 #define RVTEST_DATA_END .align 4;
     99 
    100 #endif