rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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amomaxu_w.S (1236B)


      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # amomaxu_d.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test amomaxu.w instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   TEST_CASE(2, a4, 0xffffffff80000000, \
     17     li a0, 0xffffffff80000000; \
     18     li a1, 0xfffffffffffff800; \
     19     la a3, amo_operand; \
     20     sw a0, 0(a3); \
     21     amomaxu.w	a4, a1, 0(a3); \
     22   )
     23 
     24   TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
     25 
     26   TEST_CASE(4, a4, 0, \
     27     li a1, 0xffffffffffffffff; \
     28     sw x0, 0(a3); \
     29     amomaxu.w	a4, a1, 0(a3); \
     30   )
     31 
     32   TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
     33 
     34   # The following two cases check that the upper 32 bits are ignored on rv64
     35   # implementations. Only enable them for rv64.
     36   #if __riscv_xlen == 64
     37   TEST_CASE(6, a4, 1, \
     38     li a0, 0x0000000000000001; \
     39     li a1, 0x8000000000000000; \
     40     la a3, amo_operand; \
     41     sw a0, 0(a3); \
     42     amomaxu.w	a4, a1, 0(a3); \
     43   )
     44 
     45   TEST_CASE(7, a5, 1, lw a5, 0(a3))
     46   #endif
     47 
     48   TEST_PASSFAIL
     49 
     50 RVTEST_CODE_END
     51 
     52   .data
     53 RVTEST_DATA_BEGIN
     54 
     55   TEST_DATA
     56 
     57 RVTEST_DATA_END
     58 
     59   .bss
     60   .align 3
     61 amo_operand:
     62   .dword 0