rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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amomin_w.S (1089B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # amomin_d.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test amomin.w instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   TEST_CASE(2, a4, 0xffffffff80000000, \
     17     li a0, 0xffffffff80000000; \
     18     li a1, 0xfffffffffffff800; \
     19     la a3, amo_operand; \
     20     sw a0, 0(a3); \
     21     amomin.w	a4, a1, 0(a3); \
     22   )
     23 
     24   TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
     25 
     26   TEST_CASE(4, a4, 0, \
     27     li a1, 0xffffffffffffffff; \
     28     sw x0, 0(a3); \
     29     amomin.w	a4, a1, 0(a3); \
     30   )
     31 
     32   TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
     33 
     34   TEST_CASE(6, a4, 1, \
     35     li a0, 0x0000000000000001; \
     36     li a1, 0x0000000080000000; \
     37     la a3, amo_operand; \
     38     sw a0, 0(a3); \
     39     amomin.w	a4, a1, 0(a3); \
     40   )
     41 
     42   TEST_CASE(7, a5, 0xffffffff80000000, lw a5, 0(a3))
     43 
     44   TEST_PASSFAIL
     45 
     46 RVTEST_CODE_END
     47 
     48   .data
     49 RVTEST_DATA_BEGIN
     50 
     51   TEST_DATA
     52 
     53 RVTEST_DATA_END
     54 
     55   .bss
     56   .align 3
     57 amo_operand:
     58   .dword 0