rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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amoor_w.S (874B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # amoor.w.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test amoor.w instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   TEST_CASE(2, a4, 0xffffffff80000000, \
     17     li a0, 0xffffffff80000000; \
     18     li a1, 0xfffffffffffff800; \
     19     la a3, amo_operand; \
     20     sw a0, 0(a3); \
     21     amoor.w	a4, a1, 0(a3); \
     22   )
     23 
     24   TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
     25 
     26   # try again after a cache miss
     27   TEST_CASE(4, a4, 0xfffffffffffff800, \
     28     li  a1, 1; \
     29     amoor.w a4, a1, 0(a3); \
     30   )
     31 
     32   TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3))
     33 
     34   TEST_PASSFAIL
     35 
     36 RVTEST_CODE_END
     37 
     38   .data
     39 RVTEST_DATA_BEGIN
     40 
     41   TEST_DATA
     42 
     43 RVTEST_DATA_END
     44 
     45   .bss
     46   .align 3
     47 amo_operand:
     48   .dword 0