rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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lrsc.S (2116B)


      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # lrsr.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test LR/SC instructions.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16 # get a unique core id
     17 la a0, coreid
     18 li a1, 1
     19 amoadd.w a2, a1, (a0)
     20 
     21 # for now, only run this on core 0
     22 1:li a3, 1
     23 bgeu a2, a3, 1b
     24 
     25 1: lw a1, (a0)
     26 bltu a1, a3, 1b
     27 
     28 # make sure that sc without a reservation fails.
     29 TEST_CASE( 2, a4, 1, \
     30   la a0, foo; \
     31   li a5, 0xdeadbeef; \
     32   sc.w a4, a5, (a0); \
     33 )
     34 
     35 # make sure the failing sc did not commit into memory
     36 TEST_CASE( 3, a4, 0, \
     37   lw a4, foo; \
     38 )
     39 
     40 #
     41 # Disable test case 4 for now. It assumes a <1K reservation granule, when
     42 # in reality any size granule is valid. After discussion in issue #315,
     43 # decided to simply disable the test for now.
     44 # (See https://github.com/riscv/riscv-tests/issues/315)
     45 #
     46 ## make sure that sc with the wrong reservation fails.
     47 ## TODO is this actually mandatory behavior?
     48 #TEST_CASE( 4, a4, 1, \
     49 #  la a0, foo; \
     50 #  la a1, fooTest3; \
     51 #  lr.w a1, (a1); \
     52 #  sc.w a4, a1, (a0); \
     53 #)
     54 
     55 #define LOG_ITERATIONS 10
     56 
     57 # have each core add its coreid+1 to foo 1024 times
     58 la a0, foo
     59 li a1, 1<<LOG_ITERATIONS
     60 addi a2, a2, 1
     61 1: lr.w a4, (a0)
     62 add a4, a4, a2
     63 sc.w a4, a4, (a0)
     64 bnez a4, 1b
     65 addi a1, a1, -1
     66 bnez a1, 1b
     67 
     68 # wait for all cores to finish
     69 la a0, barrier
     70 li a1, 1
     71 amoadd.w x0, a1, (a0)
     72 1: lw a1, (a0)
     73 blt a1, a3, 1b
     74 fence
     75 
     76 # expected result is 512*ncores*(ncores+1)
     77 TEST_CASE( 5, a0, 0, \
     78   lw a0, foo; \
     79   slli a1, a3, LOG_ITERATIONS-1; \
     80 1:sub a0, a0, a1; \
     81   addi a3, a3, -1; \
     82   bgez a3, 1b
     83 )
     84 
     85 # make sure that sc-after-successful-sc fails.
     86 TEST_CASE( 6, a1, 2, \
     87   la a0, foo; \
     88 1:lr.w a1, (a0); \
     89   sc.w a1, x0, (a0); \
     90   bnez a1, 1b; \
     91   sc.w a1, x0, (a0); \
     92   /* make sure that sc-after-failed-sc fails, too */ \
     93   sc.w a2, x0, (a0); \
     94   add a1, a1, a2
     95 )
     96 
     97 TEST_PASSFAIL
     98 
     99 RVTEST_CODE_END
    100 
    101   .data
    102 RVTEST_DATA_BEGIN
    103 
    104   TEST_DATA
    105 
    106 coreid: .word 0
    107 barrier: .word 0
    108 foo: .word 0
    109 .skip 1024
    110 fooTest3: .word 0
    111 RVTEST_DATA_END