rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
Log | Files | Refs | LICENSE

fclass.S (1140B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # fclass.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test fclass.d instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64UF
     14 RVTEST_CODE_BEGIN
     15 
     16   # Replace the function with the 32-bit variant defined in test_macros.h
     17   #undef TEST_FCLASS_D
     18   #define TEST_FCLASS_D TEST_FCLASS_D32
     19 
     20   #-------------------------------------------------------------
     21   # Arithmetic tests
     22   #-------------------------------------------------------------
     23 
     24   TEST_FCLASS_D( 2, 1 << 0, nInfd )
     25   TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 )
     26   TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff )
     27   TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 )
     28   TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 )
     29   TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff )
     30   TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 )
     31   TEST_FCLASS_D( 9, 1 << 7, Infd )
     32   TEST_FCLASS_D(10, 1 << 8, sNaNd )
     33   TEST_FCLASS_D(11, 1 << 9, qNaNd )
     34 
     35   TEST_PASSFAIL
     36 
     37 RVTEST_CODE_END
     38 
     39   .data
     40 RVTEST_DATA_BEGIN
     41 
     42   TEST_DATA
     43 
     44 RVTEST_DATA_END