rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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fcvt.S (1342B)


      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # fcvt.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test fcvt.d.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64UF
     14 RVTEST_CODE_BEGIN
     15 
     16   # Replace the function with the 32-bit variant defined in test_macros.h
     17   #undef TEST_INT_FP_OP_D
     18   #define TEST_INT_FP_OP_D TEST_INT_FP_OP_D32
     19 
     20   #undef TEST_FCVT_S_D
     21   #define TEST_FCVT_S_D TEST_FCVT_S_D32
     22 
     23   #-------------------------------------------------------------
     24   # Arithmetic tests
     25   #-------------------------------------------------------------
     26 
     27   TEST_INT_FP_OP_D(2,  fcvt.d.w,                   2.0,  2);
     28   TEST_INT_FP_OP_D(3,  fcvt.d.w,                  -2.0, -2);
     29 
     30   TEST_INT_FP_OP_D(4, fcvt.d.wu,                   2.0,  2);
     31   TEST_INT_FP_OP_D(5, fcvt.d.wu,            4294967294, -2);
     32 
     33   TEST_FCVT_S_D(10, -1.5, -1.5)
     34   TEST_FCVT_D_S(11, -1.5, -1.5)
     35 
     36   TEST_CASE_D32(12, a0, a1, qNaNd,
     37     la a1, test_data_22;
     38     fld f2, 0(a1);
     39     fcvt.s.d f2, f2;
     40     fcvt.d.s f2, f2;
     41     fsd f2, 0(a1);
     42     lw a0, 0(a1);
     43     lw a1, 4(a1)
     44   )
     45 
     46   TEST_PASSFAIL
     47 
     48 RVTEST_CODE_END
     49 
     50   .data
     51 RVTEST_DATA_BEGIN
     52 
     53   TEST_DATA
     54 
     55 test_data_22:
     56   .dword 0x7ffcffffffff8004
     57 
     58 RVTEST_DATA_END