rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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fdiv.S (1477B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # fdiv.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test f{div|sqrt}.d instructions.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64UF
     14 RVTEST_CODE_BEGIN
     15 
     16   # Replace the functions with the 32-bit variants defined in test_macros.h
     17   #undef TEST_FP_OP2_D
     18   #define TEST_FP_OP2_D TEST_FP_OP2_D32
     19 
     20   #undef TEST_FP_OP1_D
     21   #define TEST_FP_OP1_D TEST_FP_OP1_D32
     22 
     23   #undef TEST_FP_OP1_D_DWORD_RESULT
     24   #define TEST_FP_OP1_D_DWORD_RESULT TEST_FP_OP1_D32_DWORD_RESULT
     25 
     26   #-------------------------------------------------------------
     27   # Arithmetic tests
     28   #-------------------------------------------------------------
     29 
     30   TEST_FP_OP2_D( 2,  fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
     31   TEST_FP_OP2_D( 3,  fdiv.d, 1,-0.9991093838555584,      -1234,     1235.1 );
     32   TEST_FP_OP2_D( 4,  fdiv.d, 0,         3.14159265, 3.14159265,        1.0 );
     33 
     34   TEST_FP_OP1_D( 5,  fsqrt.d, 1, 1.7724538498928541, 3.14159265 );
     35   TEST_FP_OP1_D( 6,  fsqrt.d, 0,                100,      10000 );
     36 
     37   TEST_FP_OP1_D_DWORD_RESULT(16,  fsqrt.d, 0x10,      0x7FF8000000000000,      -1.0 );
     38 
     39   TEST_FP_OP1_D( 7,  fsqrt.d, 1, 13.076696830622021, 171.0);
     40 
     41   TEST_FP_OP1_D( 8,  fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7);
     42 
     43   TEST_PASSFAIL
     44 
     45 RVTEST_CODE_END
     46 
     47   .data
     48 RVTEST_DATA_BEGIN
     49 
     50   TEST_DATA
     51 
     52 RVTEST_DATA_END