rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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ldst.S (1143B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # ldst.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # This test verifies that flw, fld, fsw, and fsd work properly.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV32UF
     14 RVTEST_CODE_BEGIN
     15 
     16   la s0, tdat
     17   TEST_CASE_D32(2, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
     18   TEST_CASE_D32(3, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
     19   TEST_CASE_D32(4, a0, a1, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
     20   TEST_CASE_D32(5, a0, a1, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
     21   TEST_CASE_D32(6, a0, a1, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
     22 
     23   TEST_PASSFAIL
     24 
     25 RVTEST_CODE_END
     26 
     27   .data
     28 RVTEST_DATA_BEGIN
     29 
     30   TEST_DATA
     31 
     32 tdat:
     33 .word 0xbf800000
     34 .word 0x40000000
     35 .word 0x40400000
     36 .word 0xc0800000
     37 .word 0xdeadbeef
     38 .word 0xcafebabe
     39 .word 0xabad1dea
     40 .word 0x1337d00d
     41 
     42 RVTEST_DATA_END