rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
Log | Files | Refs | LICENSE

fadd.S (1386B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # fadd.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test f{add|sub|mul}.s instructions.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64UF
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_FP_OP2_S( 2,  fadd.s, 0,                3.5,        2.5,        1.0 );
     21   TEST_FP_OP2_S( 3,  fadd.s, 1,              -1234,    -1235.1,        1.1 );
     22   TEST_FP_OP2_S( 4,  fadd.s, 1,         3.14159265, 3.14159265, 0.00000001 );
     23 
     24   TEST_FP_OP2_S( 5,  fsub.s, 0,                1.5,        2.5,        1.0 );
     25   TEST_FP_OP2_S( 6,  fsub.s, 1,              -1234,    -1235.1,       -1.1 );
     26   TEST_FP_OP2_S( 7,  fsub.s, 1,         3.14159265, 3.14159265, 0.00000001 );
     27 
     28   TEST_FP_OP2_S( 8,  fmul.s, 0,                2.5,        2.5,        1.0 );
     29   TEST_FP_OP2_S( 9,  fmul.s, 1,            1358.61,    -1235.1,       -1.1 );
     30   TEST_FP_OP2_S(10,  fmul.s, 1,      3.14159265e-8, 3.14159265, 0.00000001 );
     31 
     32   # Is the canonical NaN generated for Inf - Inf?
     33   TEST_FP_OP2_S_HEX(11,  fsub.s, 0x10, qNaNf, Inff, Inff);
     34 
     35   TEST_PASSFAIL
     36 
     37 RVTEST_CODE_END
     38 
     39   .data
     40 RVTEST_DATA_BEGIN
     41 
     42   TEST_DATA
     43 
     44 RVTEST_DATA_END