rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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fclass.S (955B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # fclass.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test fclass.s instructions.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64UF
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_FCLASS_S( 2, 1 << 0, nInff )
     21   TEST_FCLASS_S( 3, 1 << 1, 0xbf800000 )
     22   TEST_FCLASS_S( 4, 1 << 2, 0x807fffff )
     23   TEST_FCLASS_S( 5, 1 << 3, 0x80000000 )
     24   TEST_FCLASS_S( 6, 1 << 4, 0x00000000 )
     25   TEST_FCLASS_S( 7, 1 << 5, 0x007fffff )
     26   TEST_FCLASS_S( 8, 1 << 6, 0x3f800000 )
     27   TEST_FCLASS_S( 9, 1 << 7, Inff )
     28   TEST_FCLASS_S(10, 1 << 8, sNaNf )
     29   TEST_FCLASS_S(11, 1 << 9, qNaNf )
     30 
     31   TEST_PASSFAIL
     32 
     33 RVTEST_CODE_END
     34 
     35   .data
     36 RVTEST_DATA_BEGIN
     37 
     38   TEST_DATA
     39 
     40 RVTEST_DATA_END