rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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fcmp.S (1426B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # fcmp.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test f{eq|lt|le}.s instructions.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64UF
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_FP_CMP_OP_S( 2, feq.s, 0x00, 1, -1.36, -1.36)
     21   TEST_FP_CMP_OP_S( 3, fle.s, 0x00, 1, -1.36, -1.36)
     22   TEST_FP_CMP_OP_S( 4, flt.s, 0x00, 0, -1.36, -1.36)
     23 
     24   TEST_FP_CMP_OP_S( 5, feq.s, 0x00, 0, -1.37, -1.36)
     25   TEST_FP_CMP_OP_S( 6, fle.s, 0x00, 1, -1.37, -1.36)
     26   TEST_FP_CMP_OP_S( 7, flt.s, 0x00, 1, -1.37, -1.36)
     27 
     28   # Only sNaN should signal invalid for feq.
     29   TEST_FP_CMP_OP_S( 8, feq.s, 0x00, 0, NaN, 0)
     30   TEST_FP_CMP_OP_S( 9, feq.s, 0x00, 0, NaN, NaN)
     31   TEST_FP_CMP_OP_S_HEX(10, feq.s, 0x10, 0, sNaNf, 0)
     32 
     33   # qNaN should signal invalid for fle/flt.
     34   TEST_FP_CMP_OP_S(11, flt.s, 0x10, 0, NaN, 0)
     35   TEST_FP_CMP_OP_S(12, flt.s, 0x10, 0, NaN, NaN)
     36   TEST_FP_CMP_OP_S_HEX(13, flt.s, 0x10, 0, sNaNf, 0)
     37   TEST_FP_CMP_OP_S(14, fle.s, 0x10, 0, NaN, 0)
     38   TEST_FP_CMP_OP_S(15, fle.s, 0x10, 0, NaN, NaN)
     39   TEST_FP_CMP_OP_S_HEX(16, fle.s, 0x10, 0, sNaNf, 0)
     40 
     41   TEST_PASSFAIL
     42 
     43 RVTEST_CODE_END
     44 
     45   .data
     46 RVTEST_DATA_BEGIN
     47 
     48   TEST_DATA
     49 
     50 RVTEST_DATA_END