rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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fcvt.S (1127B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # fcvt.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64UF
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_INT_FP_OP_S( 2,  fcvt.s.w,                   2.0,  2);
     21   TEST_INT_FP_OP_S( 3,  fcvt.s.w,                  -2.0, -2);
     22 
     23   TEST_INT_FP_OP_S( 4, fcvt.s.wu,                   2.0,  2);
     24   TEST_INT_FP_OP_S( 5, fcvt.s.wu,           4.2949673e9, -2);
     25 
     26 #if __riscv_xlen >= 64
     27   TEST_INT_FP_OP_S( 6,  fcvt.s.l,                   2.0,  2);
     28   TEST_INT_FP_OP_S( 7,  fcvt.s.l,                  -2.0, -2);
     29 
     30   TEST_INT_FP_OP_S( 8, fcvt.s.lu,                   2.0,  2);
     31   TEST_INT_FP_OP_S( 9, fcvt.s.lu,          1.8446744e19, -2);
     32 #endif
     33 
     34   TEST_PASSFAIL
     35 
     36 RVTEST_CODE_END
     37 
     38   .data
     39 RVTEST_DATA_BEGIN
     40 
     41   TEST_DATA
     42 
     43 RVTEST_DATA_END