rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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fdiv.S (1054B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # fdiv.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test f{div|sqrt}.s instructions.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64UF
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_FP_OP2_S(2,  fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
     21   TEST_FP_OP2_S(3,  fdiv.s, 1,-0.9991093838555584,      -1234,     1235.1 );
     22   TEST_FP_OP2_S(4,  fdiv.s, 0,         3.14159265, 3.14159265,        1.0 );
     23 
     24   TEST_FP_OP1_S(5,  fsqrt.s, 1, 1.7724538498928541, 3.14159265 );
     25   TEST_FP_OP1_S(6,  fsqrt.s, 0,                100,      10000 );
     26 
     27   TEST_FP_OP1_S_DWORD_RESULT(7,  fsqrt.s, 0x10, 0x7FC00000, -1.0 );
     28 
     29   TEST_FP_OP1_S(8,  fsqrt.s, 1, 13.076696, 171.0);
     30 
     31   TEST_PASSFAIL
     32 
     33 RVTEST_CODE_END
     34 
     35   .data
     36 RVTEST_DATA_BEGIN
     37 
     38   TEST_DATA
     39 
     40 RVTEST_DATA_END