rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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ldst.S (769B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # ldst.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # This test verifies that flw, fld, fsw, and fsd work properly.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV32UF
     14 RVTEST_CODE_BEGIN
     15 
     16   TEST_CASE(2, a0, 0x40000000, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); lw a0, 20(a1))
     17   TEST_CASE(3, a0, 0xbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); lw a0, 24(a1))
     18 
     19   TEST_PASSFAIL
     20 
     21 RVTEST_CODE_END
     22 
     23   .data
     24 RVTEST_DATA_BEGIN
     25 
     26   TEST_DATA
     27 
     28 tdat:
     29 .word 0xbf800000
     30 .word 0x40000000
     31 .word 0x40400000
     32 .word 0xc0800000
     33 .word 0xdeadbeef
     34 .word 0xcafebabe
     35 .word 0xabad1dea
     36 .word 0x1337d00d
     37 
     38 RVTEST_DATA_END