rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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auipc.S (644B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # auipc.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test auipc instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   TEST_CASE(2, a0, 10000, \
     17     .align 3; \
     18     lla a0, 1f + 10000; \
     19     jal a1, 1f; \
     20     1: sub a0, a0, a1; \
     21   )
     22 
     23   TEST_CASE(3, a0, -10000, \
     24     .align 3; \
     25     lla a0, 1f - 10000; \
     26     jal a1, 1f; \
     27     1: sub a0, a0, a1; \
     28   )
     29 
     30   TEST_PASSFAIL
     31 
     32 RVTEST_CODE_END
     33 
     34   .data
     35 RVTEST_DATA_BEGIN
     36 
     37   TEST_DATA
     38 
     39 RVTEST_DATA_END