rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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bge.S (2149B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # bge.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test bge instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Branch tests
     18   #-------------------------------------------------------------
     19 
     20   # Each test checks both forward and backward branches
     21 
     22   TEST_BR2_OP_TAKEN( 2, bge,  0,  0 );
     23   TEST_BR2_OP_TAKEN( 3, bge,  1,  1 );
     24   TEST_BR2_OP_TAKEN( 4, bge, -1, -1 );
     25   TEST_BR2_OP_TAKEN( 5, bge,  1,  0 );
     26   TEST_BR2_OP_TAKEN( 6, bge,  1, -1 );
     27   TEST_BR2_OP_TAKEN( 7, bge, -1, -2 );
     28 
     29   TEST_BR2_OP_NOTTAKEN(  8, bge,  0,  1 );
     30   TEST_BR2_OP_NOTTAKEN(  9, bge, -1,  1 );
     31   TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 );
     32   TEST_BR2_OP_NOTTAKEN( 11, bge, -2,  1 );
     33 
     34   #-------------------------------------------------------------
     35   # Bypassing tests
     36   #-------------------------------------------------------------
     37 
     38   TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 );
     39   TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 );
     40   TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 );
     41   TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 );
     42   TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 );
     43   TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 );
     44 
     45   TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 );
     46   TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 );
     47   TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 );
     48   TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 );
     49   TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 );
     50   TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 );
     51 
     52   #-------------------------------------------------------------
     53   # Test delay slot instructions not executed nor bypassed
     54   #-------------------------------------------------------------
     55 
     56   TEST_CASE( 24, x1, 3, \
     57     li  x1, 1; \
     58     bge x1, x0, 1f; \
     59     addi x1, x1, 1; \
     60     addi x1, x1, 1; \
     61     addi x1, x1, 1; \
     62     addi x1, x1, 1; \
     63 1:  addi x1, x1, 1; \
     64     addi x1, x1, 1; \
     65   )
     66 
     67   TEST_PASSFAIL
     68 
     69 RVTEST_CODE_END
     70 
     71   .data
     72 RVTEST_DATA_BEGIN
     73 
     74   TEST_DATA
     75 
     76 RVTEST_DATA_END