rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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fence_i.S (858B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # fence_i.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test self-modifying code and the fence.i instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16 li a3, 111
     17 lh a0, insn
     18 lh a1, insn+2
     19 
     20 # test I$ hit
     21 .align 6
     22 sh a0, 2f, t0
     23 sh a1, 2f+2, t0
     24 fence.i
     25 
     26 la a5, 2f
     27 jalr t1, a5, 0
     28 TEST_CASE( 2, a3, 444, nop )
     29 
     30 # test prefetcher hit
     31 li a4, 100
     32 1: addi a4, a4, -1
     33 bnez a4, 1b
     34 
     35 sh a0, 3f, t0
     36 sh a1, 3f+2, t0
     37 fence.i
     38 
     39 .align 6
     40 la a5, 3f
     41 jalr t1, a5, 0
     42 TEST_CASE( 3, a3, 777, nop )
     43 
     44 TEST_PASSFAIL
     45 
     46 RVTEST_CODE_END
     47 
     48   .data
     49 RVTEST_DATA_BEGIN
     50 
     51   TEST_DATA
     52 
     53 insn:
     54   addi a3, a3, 333
     55 
     56 2: addi a3, a3, 222
     57 jalr a5, t1, 0
     58 
     59 3: addi a3, a3, 555
     60 jalr a5, t1, 0
     61 
     62 RVTEST_DATA_END