rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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jal.S (1087B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # jal.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test jal instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Test 2: Basic test
     18   #-------------------------------------------------------------
     19 
     20 test_2:
     21   li  TESTNUM, 2
     22   li  ra, 0
     23 
     24   jal x4, target_2
     25 linkaddr_2:
     26   nop
     27   nop
     28 
     29   j fail
     30 
     31 target_2:
     32   la  x2, linkaddr_2
     33   bne x2, x4, fail
     34 
     35   #-------------------------------------------------------------
     36   # Test delay slot instructions not executed nor bypassed
     37   #-------------------------------------------------------------
     38 
     39   TEST_CASE( 3, ra, 3, \
     40     li  ra, 1; \
     41     jal x0, 1f; \
     42     addi ra, ra, 1; \
     43     addi ra, ra, 1; \
     44     addi ra, ra, 1; \
     45     addi ra, ra, 1; \
     46 1:  addi ra, ra, 1; \
     47     addi ra, ra, 1; \
     48   )
     49 
     50   TEST_PASSFAIL
     51 
     52 RVTEST_CODE_END
     53 
     54   .data
     55 RVTEST_DATA_BEGIN
     56 
     57   TEST_DATA
     58 
     59 RVTEST_DATA_END