rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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jalr.S (1735B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # jalr.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test jalr instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Test 2: Basic test
     18   #-------------------------------------------------------------
     19 
     20 test_2:
     21   li  TESTNUM, 2
     22   li  t0, 0
     23   la  t1, target_2
     24 
     25   jalr t0, t1, 0
     26 linkaddr_2:
     27   j fail
     28 
     29 target_2:
     30   la  t1, linkaddr_2
     31   bne t0, t1, fail
     32 
     33   #-------------------------------------------------------------
     34   # Test 3: Basic test2, rs = rd
     35   #-------------------------------------------------------------
     36 
     37 test_3:
     38   li  TESTNUM, 3
     39   la  t0, target_3
     40 
     41   jalr t0, t0, 0
     42 linkaddr_3:
     43   j fail
     44 
     45 target_3:
     46   la  t1, linkaddr_3
     47   bne t0, t1, fail
     48 
     49   #-------------------------------------------------------------
     50   # Bypassing tests
     51   #-------------------------------------------------------------
     52 
     53   TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
     54   TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
     55   TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
     56 
     57   #-------------------------------------------------------------
     58   # Test delay slot instructions not executed nor bypassed
     59   #-------------------------------------------------------------
     60 
     61   .option push
     62   .align 2
     63   .option norvc
     64   TEST_CASE( 7, t0, 4, \
     65     li  t0, 1; \
     66     la  t1, 1f; \
     67     jr  t1, -4; \
     68     addi t0, t0, 1; \
     69     addi t0, t0, 1; \
     70     addi t0, t0, 1; \
     71     addi t0, t0, 1; \
     72 1:  addi t0, t0, 1; \
     73     addi t0, t0, 1; \
     74   )
     75   .option pop
     76 
     77   TEST_PASSFAIL
     78 
     79 RVTEST_CODE_END
     80 
     81   .data
     82 RVTEST_DATA_BEGIN
     83 
     84   TEST_DATA
     85 
     86 RVTEST_DATA_END