rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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lui.S (865B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # lui.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test lui instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Basic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_CASE( 2, x1, 0x0000000000000000, lui x1, 0x00000 );
     21   TEST_CASE( 3, x1, 0xfffffffffffff800, lui x1, 0xfffff;sra x1,x1,1);
     22   TEST_CASE( 4, x1, 0x00000000000007ff, lui x1, 0x7ffff;sra x1,x1,20);
     23   TEST_CASE( 5, x1, 0xfffffffffffff800, lui x1, 0x80000;sra x1,x1,20);
     24 
     25   TEST_CASE( 6, x0, 0, lui x0, 0x80000 );
     26 
     27   TEST_PASSFAIL
     28 
     29 RVTEST_CODE_END
     30 
     31   .data
     32 RVTEST_DATA_BEGIN
     33 
     34   TEST_DATA
     35 
     36 RVTEST_DATA_END