rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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lw.S (2308B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # lw.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test lw instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Basic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_LD_OP( 2, lw, 0x0000000000ff00ff, 0,  tdat );
     21   TEST_LD_OP( 3, lw, 0xffffffffff00ff00, 4,  tdat );
     22   TEST_LD_OP( 4, lw, 0x000000000ff00ff0, 8,  tdat );
     23   TEST_LD_OP( 5, lw, 0xfffffffff00ff00f, 12, tdat );
     24 
     25   # Test with negative offset
     26 
     27   TEST_LD_OP( 6, lw, 0x0000000000ff00ff, -12, tdat4 );
     28   TEST_LD_OP( 7, lw, 0xffffffffff00ff00, -8,  tdat4 );
     29   TEST_LD_OP( 8, lw, 0x000000000ff00ff0, -4,  tdat4 );
     30   TEST_LD_OP( 9, lw, 0xfffffffff00ff00f, 0,   tdat4 );
     31 
     32   # Test with a negative base
     33 
     34   TEST_CASE( 10, x5, 0x0000000000ff00ff, \
     35     la  x1, tdat; \
     36     addi x1, x1, -32; \
     37     lw x5, 32(x1); \
     38   )
     39 
     40   # Test with unaligned base
     41 
     42   TEST_CASE( 11, x5, 0xffffffffff00ff00, \
     43     la  x1, tdat; \
     44     addi x1, x1, -3; \
     45     lw x5, 7(x1); \
     46   )
     47 
     48   #-------------------------------------------------------------
     49   # Bypassing tests
     50   #-------------------------------------------------------------
     51 
     52   TEST_LD_DEST_BYPASS( 12, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
     53   TEST_LD_DEST_BYPASS( 13, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
     54   TEST_LD_DEST_BYPASS( 14, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
     55 
     56   TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
     57   TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
     58   TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
     59 
     60   #-------------------------------------------------------------
     61   # Test write-after-write hazard
     62   #-------------------------------------------------------------
     63 
     64   TEST_CASE( 18, x2, 2, \
     65     la  x5, tdat; \
     66     lw  x2, 0(x5); \
     67     li  x2, 2; \
     68   )
     69 
     70   TEST_CASE( 19, x2, 2, \
     71     la  x5, tdat; \
     72     lw  x2, 0(x5); \
     73     nop; \
     74     li  x2, 2; \
     75   )
     76 
     77   TEST_PASSFAIL
     78 
     79 RVTEST_CODE_END
     80 
     81   .data
     82 RVTEST_DATA_BEGIN
     83 
     84   TEST_DATA
     85 
     86 tdat:
     87 tdat1:  .word 0x00ff00ff
     88 tdat2:  .word 0xff00ff00
     89 tdat3:  .word 0x0ff00ff0
     90 tdat4:  .word 0xf00ff00f
     91 
     92 RVTEST_DATA_END