rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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ori.S (1829B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # ori.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test ori instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Logical tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_IMM_OP( 2, ori, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f );
     21   TEST_IMM_OP( 3, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
     22   TEST_IMM_OP( 4, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
     23   TEST_IMM_OP( 5, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
     24 
     25   #-------------------------------------------------------------
     26   # Source/Destination tests
     27   #-------------------------------------------------------------
     28 
     29   TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 );
     30 
     31   #-------------------------------------------------------------
     32   # Bypassing tests
     33   #-------------------------------------------------------------
     34 
     35   TEST_IMM_DEST_BYPASS( 7,  0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
     36   TEST_IMM_DEST_BYPASS( 8,  1, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
     37   TEST_IMM_DEST_BYPASS( 9,  2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
     38 
     39   TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
     40   TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffffffffffff, 0x0000000000ff00ff, 0xf0f );
     41   TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
     42 
     43   TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 );
     44   TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f );
     45 
     46   TEST_PASSFAIL
     47 
     48 RVTEST_CODE_END
     49 
     50   .data
     51 RVTEST_DATA_BEGIN
     52 
     53   TEST_DATA
     54 
     55 RVTEST_DATA_END