rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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sh.S (2642B)


      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # sh.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test sh instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Basic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat );
     21   TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat );
     22   TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat );
     23   TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat );
     24 
     25   # Test with negative offset
     26 
     27   TEST_ST_OP( 6, lh, sh, 0x00000000000000aa, -6, tdat8 );
     28   TEST_ST_OP( 7, lh, sh, 0xffffffffffffaa00, -4, tdat8 );
     29   TEST_ST_OP( 8, lh, sh, 0x0000000000000aa0, -2, tdat8 );
     30   TEST_ST_OP( 9, lh, sh, 0xffffffffffffa00a, 0,  tdat8 );
     31 
     32   # Test with a negative base
     33 
     34   TEST_CASE( 10, x5, 0x5678, \
     35     la  x1, tdat9; \
     36     li  x2, 0x12345678; \
     37     addi x4, x1, -32; \
     38     sh x2, 32(x4); \
     39     lh x5, 0(x1); \
     40   )
     41 
     42   # Test with unaligned base
     43 
     44   TEST_CASE( 11, x5, 0x3098, \
     45     la  x1, tdat9; \
     46     li  x2, 0x00003098; \
     47     addi x1, x1, -5; \
     48     sh x2, 7(x1); \
     49     la  x4, tdat10; \
     50     lh x5, 0(x4); \
     51   )
     52 
     53   #-------------------------------------------------------------
     54   # Bypassing tests
     55   #-------------------------------------------------------------
     56 
     57   TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffffffffffccdd, 0,  tdat );
     58   TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffffffffffbccd, 2,  tdat );
     59   TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffffffffffbbcc, 4,  tdat );
     60   TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffffffffffabbc, 6, tdat );
     61   TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffffffffffaabb, 8, tdat );
     62   TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffffffffffdaab, 10, tdat );
     63 
     64   TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0,  tdat );
     65   TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2,  tdat );
     66   TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4,  tdat );
     67   TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat );
     68   TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
     69   TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
     70 
     71   li a0, 0xbeef
     72   la a1, tdat
     73   sh a0, 6(a1)
     74 
     75   TEST_PASSFAIL
     76 
     77 RVTEST_CODE_END
     78 
     79   .data
     80 RVTEST_DATA_BEGIN
     81 
     82   TEST_DATA
     83 
     84 tdat:
     85 tdat1:  .half 0xbeef
     86 tdat2:  .half 0xbeef
     87 tdat3:  .half 0xbeef
     88 tdat4:  .half 0xbeef
     89 tdat5:  .half 0xbeef
     90 tdat6:  .half 0xbeef
     91 tdat7:  .half 0xbeef
     92 tdat8:  .half 0xbeef
     93 tdat9:  .half 0xbeef
     94 tdat10: .half 0xbeef
     95 
     96 RVTEST_DATA_END