rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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simple.S (560B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # simple.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # This is the most basic self checking test. If your simulator does not
      8 # pass thiss then there is little chance that it will pass any of the
      9 # more complicated self checking tests.
     10 #
     11 
     12 #include "riscv_test.h"
     13 #include "test_macros.h"
     14 
     15 RVTEST_RV64U
     16 RVTEST_CODE_BEGIN
     17 
     18 RVTEST_PASS
     19 
     20 RVTEST_CODE_END
     21 
     22   .data
     23 RVTEST_DATA_BEGIN
     24 
     25   TEST_DATA
     26 
     27 RVTEST_DATA_END