rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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sll.S (4229B)


      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # sll.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test sll instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_RR_OP( 2,  sll, 0x0000000000000001, 0x0000000000000001, 0  );
     21   TEST_RR_OP( 3,  sll, 0x0000000000000002, 0x0000000000000001, 1  );
     22   TEST_RR_OP( 4,  sll, 0x0000000000000080, 0x0000000000000001, 7  );
     23   TEST_RR_OP( 5,  sll, 0x0000000000004000, 0x0000000000000001, 14 );
     24   TEST_RR_OP( 6,  sll, 0x0000000080000000, 0x0000000000000001, 31 );
     25 
     26   TEST_RR_OP( 7,  sll, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
     27   TEST_RR_OP( 8,  sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1  );
     28   TEST_RR_OP( 9,  sll, 0xffffffffffffff80, 0xffffffffffffffff, 7  );
     29   TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
     30   TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 );
     31 
     32   TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0  );
     33   TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1  );
     34   TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7  );
     35   TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 );
     36   TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 );
     37 
     38   # Verify that shifts only use bottom six(rv64) or five(rv32) bits
     39 
     40   TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
     41   TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 );
     42   TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 );
     43   TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce );
     44 
     45 #if __riscv_xlen == 64
     46   TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff );
     47   TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 );
     48   TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 );
     49   TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 );
     50 #endif
     51 
     52   #-------------------------------------------------------------
     53   # Source/Destination tests
     54   #-------------------------------------------------------------
     55 
     56   TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7  );
     57   TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 );
     58   TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 );
     59 
     60   #-------------------------------------------------------------
     61   # Bypassing tests
     62   #-------------------------------------------------------------
     63 
     64   TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
     65   TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
     66   TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
     67 
     68   TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
     69   TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
     70   TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
     71   TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
     72   TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
     73   TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
     74 
     75   TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
     76   TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
     77   TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
     78   TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
     79   TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
     80   TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
     81 
     82   TEST_RR_ZEROSRC1( 40, sll, 0, 15 );
     83   TEST_RR_ZEROSRC2( 41, sll, 32, 32 );
     84   TEST_RR_ZEROSRC12( 42, sll, 0 );
     85   TEST_RR_ZERODEST( 43, sll, 1024, 2048 );
     86 
     87   TEST_PASSFAIL
     88 
     89 RVTEST_CODE_END
     90 
     91   .data
     92 RVTEST_DATA_BEGIN
     93 
     94   TEST_DATA
     95 
     96 RVTEST_DATA_END