rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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slli.S (2827B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # slli.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test slli instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_IMM_OP( 2,  slli, 0x0000000000000001, 0x0000000000000001, 0  );
     21   TEST_IMM_OP( 3,  slli, 0x0000000000000002, 0x0000000000000001, 1  );
     22   TEST_IMM_OP( 4,  slli, 0x0000000000000080, 0x0000000000000001, 7  );
     23   TEST_IMM_OP( 5,  slli, 0x0000000000004000, 0x0000000000000001, 14 );
     24   TEST_IMM_OP( 6,  slli, 0x0000000080000000, 0x0000000000000001, 31 );
     25 
     26   TEST_IMM_OP( 7,  slli, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
     27   TEST_IMM_OP( 8,  slli, 0xfffffffffffffffe, 0xffffffffffffffff, 1  );
     28   TEST_IMM_OP( 9,  slli, 0xffffffffffffff80, 0xffffffffffffffff, 7  );
     29   TEST_IMM_OP( 10, slli, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
     30   TEST_IMM_OP( 11, slli, 0xffffffff80000000, 0xffffffffffffffff, 31 );
     31 
     32   TEST_IMM_OP( 12, slli, 0x0000000021212121, 0x0000000021212121, 0  );
     33   TEST_IMM_OP( 13, slli, 0x0000000042424242, 0x0000000021212121, 1  );
     34   TEST_IMM_OP( 14, slli, 0x0000001090909080, 0x0000000021212121, 7  );
     35   TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 );
     36   TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 );
     37 
     38 #if __riscv_xlen == 64
     39   TEST_IMM_OP( 50, slli, 0x8000000000000000, 0x0000000000000001, 63 );
     40   TEST_IMM_OP( 51, slli, 0xffffff8000000000, 0xffffffffffffffff, 39 );
     41   TEST_IMM_OP( 52, slli, 0x0909080000000000, 0x0000000021212121, 43 );
     42 #endif
     43 
     44   #-------------------------------------------------------------
     45   # Source/Destination tests
     46   #-------------------------------------------------------------
     47 
     48   TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 );
     49 
     50   #-------------------------------------------------------------
     51   # Bypassing tests
     52   #-------------------------------------------------------------
     53 
     54   TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x0000000000000080, 0x0000000000000001, 7  );
     55   TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
     56   TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
     57 
     58   TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x0000000000000080, 0x0000000000000001, 7  );
     59   TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
     60   TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
     61 
     62   TEST_IMM_ZEROSRC1( 24, slli, 0, 31 );
     63   TEST_IMM_ZERODEST( 25, slli, 33, 20 );
     64 
     65   TEST_PASSFAIL
     66 
     67 RVTEST_CODE_END
     68 
     69   .data
     70 RVTEST_DATA_BEGIN
     71 
     72   TEST_DATA
     73 
     74 RVTEST_DATA_END