rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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sltu.S (2748B)


      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # sltu.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test sltu instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_RR_OP( 2,  sltu, 0, 0x00000000, 0x00000000 );
     21   TEST_RR_OP( 3,  sltu, 0, 0x00000001, 0x00000001 );
     22   TEST_RR_OP( 4,  sltu, 1, 0x00000003, 0x00000007 );
     23   TEST_RR_OP( 5,  sltu, 0, 0x00000007, 0x00000003 );
     24 
     25   TEST_RR_OP( 6,  sltu, 1, 0x00000000, 0xffff8000 );
     26   TEST_RR_OP( 7,  sltu, 0, 0x80000000, 0x00000000 );
     27   TEST_RR_OP( 8,  sltu, 1, 0x80000000, 0xffff8000 );
     28 
     29   TEST_RR_OP( 9,  sltu, 1, 0x00000000, 0x00007fff );
     30   TEST_RR_OP( 10, sltu, 0, 0x7fffffff, 0x00000000 );
     31   TEST_RR_OP( 11, sltu, 0, 0x7fffffff, 0x00007fff );
     32 
     33   TEST_RR_OP( 12, sltu, 0, 0x80000000, 0x00007fff );
     34   TEST_RR_OP( 13, sltu, 1, 0x7fffffff, 0xffff8000 );
     35 
     36   TEST_RR_OP( 14, sltu, 1, 0x00000000, 0xffffffff );
     37   TEST_RR_OP( 15, sltu, 0, 0xffffffff, 0x00000001 );
     38   TEST_RR_OP( 16, sltu, 0, 0xffffffff, 0xffffffff );
     39 
     40   #-------------------------------------------------------------
     41   # Source/Destination tests
     42   #-------------------------------------------------------------
     43 
     44   TEST_RR_SRC1_EQ_DEST( 17, sltu, 0, 14, 13 );
     45   TEST_RR_SRC2_EQ_DEST( 18, sltu, 1, 11, 13 );
     46   TEST_RR_SRC12_EQ_DEST( 19, sltu, 0, 13 );
     47 
     48   #-------------------------------------------------------------
     49   # Bypassing tests
     50   #-------------------------------------------------------------
     51 
     52   TEST_RR_DEST_BYPASS( 20, 0, sltu, 1, 11, 13 );
     53   TEST_RR_DEST_BYPASS( 21, 1, sltu, 0, 14, 13 );
     54   TEST_RR_DEST_BYPASS( 22, 2, sltu, 1, 12, 13 );
     55 
     56   TEST_RR_SRC12_BYPASS( 23, 0, 0, sltu, 0, 14, 13 );
     57   TEST_RR_SRC12_BYPASS( 24, 0, 1, sltu, 1, 11, 13 );
     58   TEST_RR_SRC12_BYPASS( 25, 0, 2, sltu, 0, 15, 13 );
     59   TEST_RR_SRC12_BYPASS( 26, 1, 0, sltu, 1, 10, 13 );
     60   TEST_RR_SRC12_BYPASS( 27, 1, 1, sltu, 0, 16, 13 );
     61   TEST_RR_SRC12_BYPASS( 28, 2, 0, sltu, 1,  9, 13 );
     62 
     63   TEST_RR_SRC21_BYPASS( 29, 0, 0, sltu, 0, 17, 13 );
     64   TEST_RR_SRC21_BYPASS( 30, 0, 1, sltu, 1,  8, 13 );
     65   TEST_RR_SRC21_BYPASS( 31, 0, 2, sltu, 0, 18, 13 );
     66   TEST_RR_SRC21_BYPASS( 32, 1, 0, sltu, 1,  7, 13 );
     67   TEST_RR_SRC21_BYPASS( 33, 1, 1, sltu, 0, 19, 13 );
     68   TEST_RR_SRC21_BYPASS( 34, 2, 0, sltu, 1,  6, 13 );
     69 
     70   TEST_RR_ZEROSRC1( 35, sltu, 1, -1 );
     71   TEST_RR_ZEROSRC2( 36, sltu, 0, -1 );
     72   TEST_RR_ZEROSRC12( 37, sltu, 0 );
     73   TEST_RR_ZERODEST( 38, sltu, 16, 30 );
     74 
     75   TEST_PASSFAIL
     76 
     77 RVTEST_CODE_END
     78 
     79   .data
     80 RVTEST_DATA_BEGIN
     81 
     82   TEST_DATA
     83 
     84 RVTEST_DATA_END