rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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sra.S (4022B)


      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # sra.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test sra instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_RR_OP( 2,  sra, 0xffffffff80000000, 0xffffffff80000000, 0  );
     21   TEST_RR_OP( 3,  sra, 0xffffffffc0000000, 0xffffffff80000000, 1  );
     22   TEST_RR_OP( 4,  sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
     23   TEST_RR_OP( 5,  sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
     24   TEST_RR_OP( 6,  sra, 0xffffffffffffffff, 0xffffffff80000001, 31 );
     25 
     26   TEST_RR_OP( 7,  sra, 0x000000007fffffff, 0x000000007fffffff, 0  );
     27   TEST_RR_OP( 8,  sra, 0x000000003fffffff, 0x000000007fffffff, 1  );
     28   TEST_RR_OP( 9,  sra, 0x0000000000ffffff, 0x000000007fffffff, 7  );
     29   TEST_RR_OP( 10, sra, 0x000000000001ffff, 0x000000007fffffff, 14 );
     30   TEST_RR_OP( 11, sra, 0x0000000000000000, 0x000000007fffffff, 31 );
     31 
     32   TEST_RR_OP( 12, sra, 0xffffffff81818181, 0xffffffff81818181, 0  );
     33   TEST_RR_OP( 13, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1  );
     34   TEST_RR_OP( 14, sra, 0xffffffffff030303, 0xffffffff81818181, 7  );
     35   TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
     36   TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 );
     37 
     38   # Verify that shifts only use bottom six(rv64) or five(rv32) bits
     39 
     40   TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 );
     41   TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 );
     42   TEST_RR_OP( 19, sra, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffc7 );
     43   TEST_RR_OP( 20, sra, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffce );
     44   TEST_RR_OP( 21, sra, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff );
     45 
     46   #-------------------------------------------------------------
     47   # Source/Destination tests
     48   #-------------------------------------------------------------
     49 
     50   TEST_RR_SRC1_EQ_DEST( 22, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
     51   TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
     52   TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 );
     53 
     54   #-------------------------------------------------------------
     55   # Bypassing tests
     56   #-------------------------------------------------------------
     57 
     58   TEST_RR_DEST_BYPASS( 25, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
     59   TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
     60   TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
     61 
     62   TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
     63   TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
     64   TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
     65   TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
     66   TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
     67   TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
     68 
     69   TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
     70   TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
     71   TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
     72   TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
     73   TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
     74   TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
     75 
     76   TEST_RR_ZEROSRC1( 40, sra, 0, 15 );
     77   TEST_RR_ZEROSRC2( 41, sra, 32, 32 );
     78   TEST_RR_ZEROSRC12( 42, sra, 0 );
     79   TEST_RR_ZERODEST( 43, sra, 1024, 2048 );
     80 
     81   TEST_PASSFAIL
     82 
     83 RVTEST_CODE_END
     84 
     85   .data
     86 RVTEST_DATA_BEGIN
     87 
     88   TEST_DATA
     89 
     90 RVTEST_DATA_END