rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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srai.S (2597B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # srai.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test srai instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_IMM_OP( 2,  srai, 0xffffff8000000000, 0xffffff8000000000, 0  );
     21   TEST_IMM_OP( 3,  srai, 0xffffffffc0000000, 0xffffffff80000000, 1  );
     22   TEST_IMM_OP( 4,  srai, 0xffffffffff000000, 0xffffffff80000000, 7  );
     23   TEST_IMM_OP( 5,  srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
     24   TEST_IMM_OP( 6,  srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
     25 
     26   TEST_IMM_OP( 7,  srai, 0x000000007fffffff, 0x000000007fffffff, 0  );
     27   TEST_IMM_OP( 8,  srai, 0x000000003fffffff, 0x000000007fffffff, 1  );
     28   TEST_IMM_OP( 9,  srai, 0x0000000000ffffff, 0x000000007fffffff, 7  );
     29   TEST_IMM_OP( 10, srai, 0x000000000001ffff, 0x000000007fffffff, 14 );
     30   TEST_IMM_OP( 11, srai, 0x0000000000000000, 0x000000007fffffff, 31 );
     31 
     32   TEST_IMM_OP( 12, srai, 0xffffffff81818181, 0xffffffff81818181, 0  );
     33   TEST_IMM_OP( 13, srai, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1  );
     34   TEST_IMM_OP( 14, srai, 0xffffffffff030303, 0xffffffff81818181, 7  );
     35   TEST_IMM_OP( 15, srai, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
     36   TEST_IMM_OP( 16, srai, 0xffffffffffffffff, 0xffffffff81818181, 31 );
     37 
     38   #-------------------------------------------------------------
     39   # Source/Destination tests
     40   #-------------------------------------------------------------
     41 
     42   TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
     43 
     44   #-------------------------------------------------------------
     45   # Bypassing tests
     46   #-------------------------------------------------------------
     47 
     48   TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7  );
     49   TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
     50   TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
     51 
     52   TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
     53   TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
     54   TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
     55 
     56   TEST_IMM_ZEROSRC1( 24, srai, 0, 4 );
     57   TEST_IMM_ZERODEST( 25, srai, 33, 10 );
     58 
     59   TEST_PASSFAIL
     60 
     61 RVTEST_CODE_END
     62 
     63   .data
     64 RVTEST_DATA_BEGIN
     65 
     66   TEST_DATA
     67 
     68 RVTEST_DATA_END