rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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srl.S (3452B)


      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # srl.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test srl instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20 #define TEST_SRL(n, v, a) \
     21   TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
     22 
     23   TEST_SRL( 2,  0xffffffff80000000, 0  );
     24   TEST_SRL( 3,  0xffffffff80000000, 1  );
     25   TEST_SRL( 4,  0xffffffff80000000, 7  );
     26   TEST_SRL( 5,  0xffffffff80000000, 14 );
     27   TEST_SRL( 6,  0xffffffff80000001, 31 );
     28 
     29   TEST_SRL( 7,  0xffffffffffffffff, 0  );
     30   TEST_SRL( 8,  0xffffffffffffffff, 1  );
     31   TEST_SRL( 9,  0xffffffffffffffff, 7  );
     32   TEST_SRL( 10, 0xffffffffffffffff, 14 );
     33   TEST_SRL( 11, 0xffffffffffffffff, 31 );
     34 
     35   TEST_SRL( 12, 0x0000000021212121, 0  );
     36   TEST_SRL( 13, 0x0000000021212121, 1  );
     37   TEST_SRL( 14, 0x0000000021212121, 7  );
     38   TEST_SRL( 15, 0x0000000021212121, 14 );
     39   TEST_SRL( 16, 0x0000000021212121, 31 );
     40 
     41   # Verify that shifts only use bottom six(rv64) or five(rv32) bits
     42 
     43   TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
     44   TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 );
     45   TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 );
     46   TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce );
     47   TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
     48 
     49   #-------------------------------------------------------------
     50   # Source/Destination tests
     51   #-------------------------------------------------------------
     52 
     53   TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7  );
     54   TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 );
     55   TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
     56 
     57   #-------------------------------------------------------------
     58   # Bypassing tests
     59   #-------------------------------------------------------------
     60 
     61   TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7  );
     62   TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 );
     63   TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 );
     64 
     65   TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7  );
     66   TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 );
     67   TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 );
     68   TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7  );
     69   TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 );
     70   TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 );
     71 
     72   TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7  );
     73   TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 );
     74   TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 );
     75   TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7  );
     76   TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 );
     77   TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 );
     78 
     79   TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
     80   TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
     81   TEST_RR_ZEROSRC12( 42, srl, 0 );
     82   TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
     83 
     84   TEST_PASSFAIL
     85 
     86 RVTEST_CODE_END
     87 
     88   .data
     89 RVTEST_DATA_BEGIN
     90 
     91   TEST_DATA
     92 
     93 RVTEST_DATA_END