rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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srli.S (2176B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # srli.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test srli instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20 #define TEST_SRLI(n, v, a) \
     21   TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
     22 
     23   TEST_SRLI( 2,  0xffffffff80000000, 0  );
     24   TEST_SRLI( 3,  0xffffffff80000000, 1  );
     25   TEST_SRLI( 4,  0xffffffff80000000, 7  );
     26   TEST_SRLI( 5,  0xffffffff80000000, 14 );
     27   TEST_SRLI( 6,  0xffffffff80000001, 31 );
     28 
     29   TEST_SRLI( 7,  0xffffffffffffffff, 0  );
     30   TEST_SRLI( 8,  0xffffffffffffffff, 1  );
     31   TEST_SRLI( 9,  0xffffffffffffffff, 7  );
     32   TEST_SRLI( 10, 0xffffffffffffffff, 14 );
     33   TEST_SRLI( 11, 0xffffffffffffffff, 31 );
     34 
     35   TEST_SRLI( 12, 0x0000000021212121, 0  );
     36   TEST_SRLI( 13, 0x0000000021212121, 1  );
     37   TEST_SRLI( 14, 0x0000000021212121, 7  );
     38   TEST_SRLI( 15, 0x0000000021212121, 14 );
     39   TEST_SRLI( 16, 0x0000000021212121, 31 );
     40 
     41   #-------------------------------------------------------------
     42   # Source/Destination tests
     43   #-------------------------------------------------------------
     44 
     45   TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 );
     46 
     47   #-------------------------------------------------------------
     48   # Bypassing tests
     49   #-------------------------------------------------------------
     50 
     51   TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7  );
     52   TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 );
     53   TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 );
     54 
     55   TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7  );
     56   TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 );
     57   TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 );
     58 
     59   TEST_IMM_ZEROSRC1( 24, srli, 0, 4 );
     60   TEST_IMM_ZERODEST( 25, srli, 33, 10 );
     61 
     62   TEST_PASSFAIL
     63 
     64 RVTEST_CODE_END
     65 
     66   .data
     67 RVTEST_DATA_BEGIN
     68 
     69   TEST_DATA
     70 
     71 RVTEST_DATA_END