rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
Log | Files | Refs | LICENSE

sw.S (2680B)


      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # sw.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test sw instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV64U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Basic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_ST_OP( 2, lw, sw, 0x0000000000aa00aa, 0,  tdat );
     21   TEST_ST_OP( 3, lw, sw, 0xffffffffaa00aa00, 4,  tdat );
     22   TEST_ST_OP( 4, lw, sw, 0x000000000aa00aa0, 8,  tdat );
     23   TEST_ST_OP( 5, lw, sw, 0xffffffffa00aa00a, 12, tdat );
     24 
     25   # Test with negative offset
     26 
     27   TEST_ST_OP( 6, lw, sw, 0x0000000000aa00aa, -12, tdat8 );
     28   TEST_ST_OP( 7, lw, sw, 0xffffffffaa00aa00, -8,  tdat8 );
     29   TEST_ST_OP( 8, lw, sw, 0x000000000aa00aa0, -4,  tdat8 );
     30   TEST_ST_OP( 9, lw, sw, 0xffffffffa00aa00a, 0,   tdat8 );
     31 
     32   # Test with a negative base
     33 
     34   TEST_CASE( 10, x5, 0x12345678, \
     35     la  x1, tdat9; \
     36     li  x2, 0x12345678; \
     37     addi x4, x1, -32; \
     38     sw x2, 32(x4); \
     39     lw x5, 0(x1); \
     40   )
     41 
     42   # Test with unaligned base
     43 
     44   TEST_CASE( 11, x5, 0x58213098, \
     45     la  x1, tdat9; \
     46     li  x2, 0x58213098; \
     47     addi x1, x1, -3; \
     48     sw x2, 7(x1); \
     49     la  x4, tdat10; \
     50     lw x5, 0(x4); \
     51   )
     52 
     53   #-------------------------------------------------------------
     54   # Bypassing tests
     55   #-------------------------------------------------------------
     56 
     57   TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xffffffffaabbccdd, 0,  tdat );
     58   TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xffffffffdaabbccd, 4,  tdat );
     59   TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xffffffffddaabbcc, 8,  tdat );
     60   TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xffffffffcddaabbc, 12, tdat );
     61   TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xffffffffccddaabb, 16, tdat );
     62   TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xffffffffbccddaab, 20, tdat );
     63 
     64   TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0,  tdat );
     65   TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4,  tdat );
     66   TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8,  tdat );
     67   TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat );
     68   TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat );
     69   TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat );
     70 
     71   TEST_PASSFAIL
     72 
     73 RVTEST_CODE_END
     74 
     75   .data
     76 RVTEST_DATA_BEGIN
     77 
     78   TEST_DATA
     79 
     80 tdat:
     81 tdat1:  .word 0xdeadbeef
     82 tdat2:  .word 0xdeadbeef
     83 tdat3:  .word 0xdeadbeef
     84 tdat4:  .word 0xdeadbeef
     85 tdat5:  .word 0xdeadbeef
     86 tdat6:  .word 0xdeadbeef
     87 tdat7:  .word 0xdeadbeef
     88 tdat8:  .word 0xdeadbeef
     89 tdat9:  .word 0xdeadbeef
     90 tdat10: .word 0xdeadbeef
     91 
     92 RVTEST_DATA_END