rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
Log | Files | Refs | LICENSE

mulhsu.S (2997B)


      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # mulhsu.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test mulhsu instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV32U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_RR_OP( 2,  mulhsu, 0x00000000, 0x00000000, 0x00000000 );
     21   TEST_RR_OP( 3,  mulhsu, 0x00000000, 0x00000001, 0x00000001 );
     22   TEST_RR_OP( 4,  mulhsu, 0x00000000, 0x00000003, 0x00000007 );
     23 
     24   TEST_RR_OP( 5,  mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
     25   TEST_RR_OP( 6,  mulhsu, 0x00000000, 0x80000000, 0x00000000 );
     26   TEST_RR_OP( 7,  mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
     27 
     28   TEST_RR_OP(30,  mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
     29   TEST_RR_OP(31,  mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
     30 
     31   TEST_RR_OP(32,  mulhsu, 0xff010000, 0xff000000, 0xff000000 );
     32 
     33   TEST_RR_OP(33,  mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
     34   TEST_RR_OP(34,  mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
     35   TEST_RR_OP(35,  mulhsu, 0x00000000, 0x00000001, 0xffffffff );
     36 
     37   #-------------------------------------------------------------
     38   # Source/Destination tests
     39   #-------------------------------------------------------------
     40 
     41   TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
     42   TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
     43   TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
     44 
     45   #-------------------------------------------------------------
     46   # Bypassing tests
     47   #-------------------------------------------------------------
     48 
     49   TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
     50   TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
     51   TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
     52 
     53   TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
     54   TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
     55   TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
     56   TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
     57   TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
     58   TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
     59 
     60   TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
     61   TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
     62   TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
     63   TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
     64   TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
     65   TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
     66 
     67   TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
     68   TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
     69   TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
     70   TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
     71 
     72 
     73 
     74   TEST_PASSFAIL
     75 
     76 RVTEST_CODE_END
     77 
     78   .data
     79 RVTEST_DATA_BEGIN
     80 
     81   TEST_DATA
     82 
     83 RVTEST_DATA_END