rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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rem.S (919B)

      1 # See LICENSE for license details.
      2 
      3 #*****************************************************************************
      4 # rem.S
      5 #-----------------------------------------------------------------------------
      6 #
      7 # Test rem instruction.
      8 #
      9 
     10 #include "riscv_test.h"
     11 #include "test_macros.h"
     12 
     13 RVTEST_RV32U
     14 RVTEST_CODE_BEGIN
     15 
     16   #-------------------------------------------------------------
     17   # Arithmetic tests
     18   #-------------------------------------------------------------
     19 
     20   TEST_RR_OP( 2, rem,  2,  20,   6 );
     21   TEST_RR_OP( 3, rem, -2, -20,   6 );
     22   TEST_RR_OP( 4, rem,  2,  20,  -6 );
     23   TEST_RR_OP( 5, rem, -2, -20,  -6 );
     24 
     25   TEST_RR_OP( 6, rem,  0, -1<<31,  1 );
     26   TEST_RR_OP( 7, rem,  0, -1<<31, -1 );
     27 
     28   TEST_RR_OP( 8, rem, -1<<31, -1<<31, 0 );
     29   TEST_RR_OP( 9, rem,      1,      1, 0 );
     30   TEST_RR_OP(10, rem,      0,      0, 0 );
     31 
     32   TEST_PASSFAIL
     33 
     34 RVTEST_CODE_END
     35 
     36   .data
     37 RVTEST_DATA_BEGIN
     38 
     39   TEST_DATA
     40 
     41 RVTEST_DATA_END