cda4210_lisp_coproc

commit 46303e07e9bda309cb451aa824680db9bdd19fe8
parent 8e17e8bc9d84fbaa5c06bf549faf754f087c8ce6
Author: vin <git@vineetk.net>
Date:   Thu, 20 Nov 2025 11:27:13 -0500

fix lint errors from icarus-verilog and verilator

Diffstat:
M
rtl/lisp_coproc.sv
 | 
15
++++++++++-----

1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/rtl/lisp_coproc.sv b/rtl/lisp_coproc.sv
@@ -1,3 +1,5 @@
+`timescale 1ns/1ps // be consistent with testbench
+
 module lisp_coproc (
     input  wire        clk,
     input  wire        rst,
@@ -33,7 +35,6 @@ module lisp_coproc (
     
     // Type Checkers
     wire is_cons_a   = (arg1_reg[7:6] == 2'b11);
-    wire is_cons_b   = (arg2_reg[7:6] == 2'b11);
     wire is_num_a    = (arg1_reg[7:6] == 2'b10);
     wire is_num_b    = (arg2_reg[7:6] == 2'b10);
     
@@ -99,10 +100,11 @@ module lisp_coproc (
             // --- MMIO Writes ---
             if (cs && !rw) begin
                 case (addr)
-                    3'h0: opcode_reg <= data_in;
-                    3'h1: arg1_reg   <= data_in;
-                    3'h2: arg2_reg   <= data_in;
-                    3'h3: result_reg <= data_in;
+                  3'h0: opcode_reg <= data_in;
+                  3'h1: arg1_reg   <= data_in;
+                  3'h2: arg2_reg   <= data_in;
+                  3'h3: result_reg <= data_in;
+		  default: ;
                 endcase
             end
             
@@ -157,6 +159,7 @@ module lisp_coproc (
                                 if (alu_sum[5:0] == 6'd0) flag_zero <= 1'b1;
                             end
                         end
+		      default: ;
                     endcase
                 end
 
@@ -183,8 +186,10 @@ module lisp_coproc (
                         8'h06: begin // ADD
                             if (!flag_err_type) result_reg <= {2'b10, alu_sum[5:0]};
                         end
+		      default: ;
                     endcase
                 end
+	      default: ;
             endcase
         end
     end