migrate from electric vlsi to librelane/sky130 flowHEADmaster

this is quite a major shift. moves the project from a manual,
full-custom layout workflow to a more modern automated flow and a more
modern process (130nm vs 350nm). also improved the testbench.
migration also resolves previous manual routing-caused errors (like
the CONS logic bug and difficulty in implementing TG
logic).

this nearly halved the transistor count from 15k to 8k and reduced
area size by 300x.

1 files changed, 2 insertions, 2 deletions

diff --git a/vlsi/tb_chip_core.v b/vlsi/tb_chip_core.v
index 66fa212..b4a8925 100644
--- a/vlsi/tb_chip_core.v
+++ b/vlsi/tb_chip_core.v
@@ -115,13 +115,13 @@ module tb_chip_core;
     // ========================================================================
 
     initial begin
-        $dumpfile("chip_core_robust.vcd");
+        $dumpfile("chip_core.vcd");
         $dumpvars(0, tb_chip_core);
         
         // --- Initialize ---
         rst = 1; cs = 0; rw = 0; addr = 0; data_in = 0;
         #20 rst = 0; #20;
-        $display("\n=== STARTING ROBUST VERIFICATION ===\n");
+        $display("\n=== STARTING VERIFICATION ===\n");
 
         // --------------------------------------------------------
         // SCENARIO 1: ALU Boundary & Overflow