| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2025-12-10 | migrate from electric vlsi to librelane/sky130 flowHEADmaster | vin | 1 | -211/+242 | |
| this is quite a major shift. moves the project from a manual, full-custom layout workflow to a more modern automated flow and a more modern process (130nm vs 350nm). also improved the testbench. migration also resolves previous manual routing-caused errors (like the CONS logic bug and difficulty in implementing TG logic). this nearly halved the transistor count from 15k to 8k and reduced area size by 300x. | |||||
| 2025-11-20 | fix lint errors from icarus-verilog and verilator | vin | 1 | -5/+10 | |
| 2025-11-20 | fix rtl, now tests all pass | vin | 1 | -188/+135 | |
| need to go through the sv files again and also run a linter | |||||
| 2025-11-20 | initial golden rtl | vin | 1 | -0/+268 | |
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index : cda4210_lisp_coproc | |
| A primitive Lisp accelerator in a full-custom physical design (Electric VLSI MOSIS 350nm) and RTL digital design (Librelane Sky130nm PDK) | Vineet K |
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