commit 6927c5bdc6009b2acb05a2a7d176003447340a34
parent be6b8ee0f4fb98234a91f7d2662462ba7ec0b295
Author: vin <git@vineetk.net>
Date: Thu, 20 Mar 2025 16:06:12 -0400
add xor instruction and PC logging
Diffstat:
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/riscvsingle.sv b/riscvsingle.sv
@@ -99,7 +99,9 @@ module my_computer(input logic clk, reset,
dmem dmem(clk, MemWrite, DataAddr, WriteData, ReadData, my_sw, my_rd);
assign my_PC = PC;
-
+
+ always_ff @(posedge clk)
+ $display("PC: %x", PC);
endmodule
// =======================================================================
@@ -275,6 +277,7 @@ module aludec(input logic opb5,
else
ALUControl = 3'b000; // add, addi
3'b010: ALUControl = 3'b101; // slt, slti
+ 3'b100: ALUControl = 3'b100; // xor, xori
3'b110: ALUControl = 3'b011; // or, ori
3'b111: ALUControl = 3'b010; // and, andi
default: ALUControl = 3'bxxx; // ???
