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| author | vin <git@vineetk.net> | 2025-03-20 16:06:12 -0400 |
|---|---|---|
| committer | vin <git@vineetk.net> | 2025-03-20 16:08:09 -0400 |
| commit | 6927c5bdc6009b2acb05a2a7d176003447340a34 (patch) | |
| tree | 88b7992a3924ffce8caba3b51a2ea56692f41247 | |
| parent | be6b8ee0f4fb98234a91f7d2662462ba7ec0b295 (diff) | |
add xor instruction and PC logging
| -rw-r--r-- | riscvsingle.sv | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/riscvsingle.sv b/riscvsingle.sv index 91fbe19..f5933ce 100644 --- a/riscvsingle.sv +++ b/riscvsingle.sv | |||
| @@ -99,7 +99,9 @@ module my_computer(input logic clk, reset, | |||
| 99 | dmem dmem(clk, MemWrite, DataAddr, WriteData, ReadData, my_sw, my_rd); | 99 | dmem dmem(clk, MemWrite, DataAddr, WriteData, ReadData, my_sw, my_rd); |
| 100 | 100 | ||
| 101 | assign my_PC = PC; | 101 | assign my_PC = PC; |
| 102 | 102 | ||
| 103 | always_ff @(posedge clk) | ||
| 104 | $display("PC: %x", PC); | ||
| 103 | endmodule | 105 | endmodule |
| 104 | 106 | ||
| 105 | // ======================================================================= | 107 | // ======================================================================= |
| @@ -275,6 +277,7 @@ module aludec(input logic opb5, | |||
| 275 | else | 277 | else |
| 276 | ALUControl = 3'b000; // add, addi | 278 | ALUControl = 3'b000; // add, addi |
| 277 | 3'b010: ALUControl = 3'b101; // slt, slti | 279 | 3'b010: ALUControl = 3'b101; // slt, slti |
| 280 | 3'b100: ALUControl = 3'b100; // xor, xori | ||
| 278 | 3'b110: ALUControl = 3'b011; // or, ori | 281 | 3'b110: ALUControl = 3'b011; // or, ori |
| 279 | 3'b111: ALUControl = 3'b010; // and, andi | 282 | 3'b111: ALUControl = 3'b010; // and, andi |
| 280 | default: ALUControl = 3'bxxx; // ??? | 283 | default: ALUControl = 3'bxxx; // ??? |
