eel3792c_rv32i - RV32I implementation on a DE10-Lite FPGA for the EEL3792C course.

Age	Commit message (Expand)	Author	Files	Lines
2025-04-17	increase rom to 128 from 64HEAD master	vin	3	-5/+103
2025-04-17	increase RAM size to 0xff	vin	2	-1/+6
2025-04-17	add makefile to compile C code easier	vin	1	-0/+15
2025-04-17	write fibonacci.c code without offset	vin	1	-2/+2
2025-04-17	zero out the ram	vin	1	-1023/+1023
2025-04-10	update fibonacci.c	vin	1	-5/+5
2025-03-31	word-align c fibonacci memory addresses	vin	1	-3/+3
2025-03-31	add riscv32 nix cross-toolchain and fibonacci c file	vin	2	-0/+15
2025-03-25	increase test bench length	vin	2	-3/+3
2025-03-25	add blt and bge	vin	1	-6/+13
2025-03-25	refactor PCSrc assignment and add bne instruction	vin	1	-1/+10
2025-03-25	fibonacci with blt and bne	jg0	2	-6/+4
2025-03-25	Fibonacci assembly code and machine code	jg0	2	-21/+33
2025-03-24	remove db and incremental_db	vin	2	-251/+251
2025-03-24	add shift instructions (sll, srl, sra, and immediates)	vin	1	-22/+28
2025-03-20	add xor instruction and PC logging	vin	1	-1/+4
2025-03-18	update .gitignore to ignore quartus directories	vin	1	-0/+3
2025-03-10	use relative filepath for ROM and RAM	vin	1	-2/+2
2025-03-10	remove auto-generated reports	vin	1	-0/+8
2025-03-10	initial payload	vin	9	-0/+1906